This problem is likely either that prefetches don't mark themselves as such, or that they do and it gets lost somewhere. I'll look at this tonight. Could you throw together a simple program that demonstrates the problem quickly?
Gabe Vince Weaver wrote: > Hello > > I tried tracking this problem down, but as usual I quickly get lost > digging through the uop generation code. > > On x86_se with the simple atomic processor, a prefetch instruction that > tries to load an invalid address aborts the simulation even when it > shouldn't. I've tested to make sure real hardware does not exhibit this > problem. > > Attached is a sample test case that does two different PREFETCH_T0_M > instructions. m5 can handle the prefetch of the valid address, but aborts > on the second one. > > This particular bug keeps most of spec2k from working on x86_64. > > Vince > ------------------------------------------------------------------------ > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
