Hello

I'm sure the correct fix will be applied before too long, but in the 
meantime if anyone is trying to run benchmarks on x86_se that use the 
prefetch instructions, the following patch will turn them into nops so you 
can make progress past the broken prefetches.

Vince

diff -r 9c33426d404a 
src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
--- a/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py     
Mon Oct 19 17:29:34 2009 -0400
+++ b/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py     
Tue Oct 20 12:48:25 2009 -0400
@@ -56,24 +56,28 @@
 microcode = '''
 def macroop PREFETCH_M
 {
-    ld t0, seg, sib, disp, dataSize=1, prefetch=True
+    fault "NoFault"
+#    ld t0, seg, sib, disp, dataSize=1, prefetch=True
 };
 
 def macroop PREFETCH_P
 {
-    rdip t7
-    ld t0, seg, riprel, disp, dataSize=1, prefetch=True
+    fault "NoFault"
+#    rdip t7
+#    ld t0, seg, riprel, disp, dataSize=1, prefetch=True
 };
 
 def macroop PREFETCH_T0_M
 {
-    ld t0, seg, sib, disp, dataSize=1, prefetch=True
+    fault "NoFault"
+#    ld t0, seg, sib, disp, dataSize=1, prefetch=True
 };
 
 def macroop PREFETCH_T0_P
 {
-    rdip t7
-    ld t0, seg, riprel, disp, dataSize=1, prefetch=True
+    fault "NoFault"
+#    rdip t7
+#    ld t0, seg, riprel, disp, dataSize=1, prefetch=True
 };
 
 '''
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev

Reply via email to