Hi everyone,
I'm getting an assertion failure in the top of
PageTable::translate(RequestPtr req) when running one of my PowerPC
binaries on O3CPU. This is the offending assertion:
assert(pageAlign(req->getVaddr() + req->getSize() - 1)
== pageAlign(req->getVaddr()));
If I comment this out and put in a DPRINTF, it turns out that the problem
is this:
39789018: system.cpu.iew.lsq.thread.0: Executing store PC 0x1002fb38
[sn:67277]
39789018: global: RegFile: Access to int register 57, has data 0xffffffff
39789018: global: RegFile: Access to int register 232, has data 0x9
39789018: global: Would fail assertion in PageTable::translate
39789018: global: Couldn't Translate: 0xffffffff
39789018: system.cpu.iew.lsq.thread.0: Fault on Store PC 0x1002fb38,
[sn:67277],
Size = 0
Later on, this store gets squashed because of a branch misprediction.
Should this assertion be failing, even for speculative instructions? If
so, then I'm guessing that I've got a problem with the store being
scheduled too early. If not, then is it safe to remove or modify the
assertion to account for speculation?
Thanks
Tim
--
The University of Edinburgh is a charitable body, registered in
Scotland, with registration number SC005336.
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev