changeset 77318ac91316 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=77318ac91316
description:
ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.
diffstat:
2 files changed, 5 insertions(+), 3 deletions(-)
src/arch/arm/intregs.hh | 2 ++
src/arch/arm/isa/operands.isa | 6 +++---
diffs (28 lines):
diff -r 36aa46630e62 -r 77318ac91316 src/arch/arm/intregs.hh
--- a/src/arch/arm/intregs.hh Sun Nov 08 01:57:34 2009 -0800
+++ b/src/arch/arm/intregs.hh Sun Nov 08 01:59:20 2009 -0800
@@ -102,6 +102,8 @@
INTREG_ZERO, // Dummy zero reg since there has to be one.
INTREG_UREG0,
+ INTREG_RHI,
+ INTREG_RLO,
NUM_INTREGS,
NUM_ARCH_INTREGS = INTREG_PC + 1,
diff -r 36aa46630e62 -r 77318ac91316 src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa Sun Nov 08 01:57:34 2009 -0800
+++ b/src/arch/arm/isa/operands.isa Sun Nov 08 01:59:20 2009 -0800
@@ -63,9 +63,9 @@
'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead,
maybePCWrite),
'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead,
maybePCWrite),
- 'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7),
- 'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8),
- 'LR': ('IntReg', 'uw', '14', 'IsInteger', 9),
+ 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
+ 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
+ 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
#Register fields for microops
'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
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