changeset 44010fc924d4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=44010fc924d4
description:
X86: Don't panic on faults on prefetches in SE mode.
diffstat:
1 file changed, 15 insertions(+), 11 deletions(-)
src/arch/x86/tlb.cc | 26 +++++++++++++++-----------
diffs (36 lines):
diff -r b3ab661715ac -r 44010fc924d4 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Sun Nov 08 22:49:57 2009 -0800
+++ b/src/arch/x86/tlb.cc Sun Nov 08 22:49:58 2009 -0800
@@ -637,17 +637,21 @@
success = p->pTable->lookup(vaddr, newEntry);
}
if (!success) {
- const char *modeStr = "";
- if (mode == Execute)
- modeStr = "execute";
- else if (mode == Read)
- modeStr = "read";
- else if (mode == Write)
- modeStr = "write";
- else
- modeStr = "?";
- panic("Tried to %s unmapped address %#x.\n",
- modeStr, vaddr);
+ if (req->isPrefetch()) {
+ return new PageFault(vaddr, true, mode, true, false);
+ } else {
+ const char *modeStr = "";
+ if (mode == Execute)
+ modeStr = "execute";
+ else if (mode == Read)
+ modeStr = "read";
+ else if (mode == Write)
+ modeStr = "write";
+ else
+ modeStr = "?";
+ panic("Tried to %s unmapped address %#x.\n",
+ modeStr, vaddr);
+ }
} else {
Addr alignedVaddr = p->pTable->pageAlign(vaddr);
DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
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