changeset 48d10ba361c9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=48d10ba361c9
description:
Mem: Eliminate the NO_FAULT request flag.
diffstat:
8 files changed, 26 insertions(+), 10 deletions(-)
src/arch/alpha/faults.cc | 2 +-
src/arch/alpha/isa/decoder.isa | 2 +-
src/arch/alpha/isa/mem.isa | 2 +-
src/arch/mips/isa/formats/mem.isa | 2 +-
src/cpu/checker/cpu.cc | 2 +-
src/cpu/simple/atomic.cc | 16 +++++++++++++---
src/cpu/simple/timing.cc | 8 ++++++++
src/mem/request.hh | 2 --
diffs (137 lines):
diff -r 44010fc924d4 -r 48d10ba361c9 src/arch/alpha/faults.cc
--- a/src/arch/alpha/faults.cc Sun Nov 08 22:49:58 2009 -0800
+++ b/src/arch/alpha/faults.cc Tue Nov 10 21:10:18 2009 -0800
@@ -144,7 +144,7 @@
// read, like the EV5). The EV6 approach is cleaner and seems to
// work with EV5 PAL code, but not the other way around.
if (!tc->misspeculating() &&
- reqFlags.noneSet(Request::VPTE|Request::NO_FAULT)) {
+ reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
// set VA register with faulting address
tc->setMiscRegNoEffect(IPR_VA, vaddr);
diff -r 44010fc924d4 -r 48d10ba361c9 src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isa Sun Nov 08 22:49:58 2009 -0800
+++ b/src/arch/alpha/isa/decoder.isa Tue Nov 10 21:10:18 2009 -0800
@@ -627,7 +627,7 @@
format MiscPrefetch {
0xf800: wh64({{ EA = Rb & ~ULL(63); }},
{{ xc->writeHint(EA, 64, memAccessFlags); }},
- mem_flags = NO_FAULT,
+ mem_flags = PREFETCH,
inst_flags = [IsMemRef, IsDataPrefetch,
IsStore, MemWriteOp]);
}
diff -r 44010fc924d4 -r 48d10ba361c9 src/arch/alpha/isa/mem.isa
--- a/src/arch/alpha/isa/mem.isa Sun Nov 08 22:49:58 2009 -0800
+++ b/src/arch/alpha/isa/mem.isa Tue Nov 10 21:10:18 2009 -0800
@@ -548,7 +548,7 @@
pf_flags = makeList(pf_flags)
inst_flags = makeList(inst_flags)
- pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
+ pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
'IsDataPrefetch', 'MemReadOp']
diff -r 44010fc924d4 -r 48d10ba361c9 src/arch/mips/isa/formats/mem.isa
--- a/src/arch/mips/isa/formats/mem.isa Sun Nov 08 22:49:58 2009 -0800
+++ b/src/arch/mips/isa/formats/mem.isa Tue Nov 10 21:10:18 2009 -0800
@@ -619,7 +619,7 @@
def format Prefetch(ea_code = {{ EA = Rs + disp; }},
mem_flags = [], pf_flags = [], inst_flags = []) {{
- pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
+ pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
'IsDataPrefetch', 'MemReadOp']
diff -r 44010fc924d4 -r 48d10ba361c9 src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc Sun Nov 08 22:49:58 2009 -0800
+++ b/src/cpu/checker/cpu.cc Tue Nov 10 21:10:18 2009 -0800
@@ -326,7 +326,7 @@
{
// Remove any dynamic flags that don't have to do with the request itself.
unsigned flags = unverifiedReq->getFlags();
- unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE |
NO_FAULT;
+ unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE |
PREFETCH;
flags = flags & (mask);
if (flags == req->getFlags()) {
return false;
diff -r 44010fc924d4 -r 48d10ba361c9 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Sun Nov 08 22:49:58 2009 -0800
+++ b/src/cpu/simple/atomic.cc Tue Nov 10 21:10:18 2009 -0800
@@ -353,8 +353,14 @@
recordEvent("Uncached Read");
//If there's a fault, return it
- if (fault != NoFault)
- return fault;
+ if (fault != NoFault) {
+ if (req->isPrefetch()) {
+ return NoFault;
+ } else {
+ return fault;
+ }
+ }
+
//If we don't need to access a second cache line, stop now.
if (secondAddr <= addr)
{
@@ -531,7 +537,11 @@
assert(locked);
locked = false;
}
- return fault;
+ if (fault != NoFault && req->isPrefetch()) {
+ return NoFault;
+ } else {
+ return fault;
+ }
}
/*
diff -r 44010fc924d4 -r 48d10ba361c9 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Sun Nov 08 22:49:58 2009 -0800
+++ b/src/cpu/simple/timing.cc Tue Nov 10 21:10:18 2009 -0800
@@ -273,6 +273,8 @@
{
_status = Running;
if (fault != NoFault) {
+ if (req->isPrefetch())
+ fault = NoFault;
delete data;
delete req;
@@ -315,6 +317,10 @@
{
_status = Running;
if (fault1 != NoFault || fault2 != NoFault) {
+ if (req1->isPrefetch())
+ fault1 = NoFault;
+ if (req2->isPrefetch())
+ fault2 = NoFault;
delete data;
delete req1;
delete req2;
@@ -360,6 +366,8 @@
void
TimingSimpleCPU::translationFault(Fault fault)
{
+ // fault may be NoFault in cases where a fault is suppressed,
+ // for instance prefetches.
numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
diff -r 44010fc924d4 -r 48d10ba361c9 src/mem/request.hh
--- a/src/mem/request.hh Sun Nov 08 22:49:58 2009 -0800
+++ b/src/mem/request.hh Tue Nov 10 21:10:18 2009 -0800
@@ -72,8 +72,6 @@
/** This request is to a memory mapped register. */
static const FlagsType MMAPED_IPR = 0x00002000;
- /** The request should not cause a page fault. */
- static const FlagsType NO_FAULT = 0x00010000;
/** The request should ignore unaligned access faults */
static const FlagsType NO_ALIGN_FAULT = 0x00020000;
/** The request should ignore unaligned access faults */
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