changeset f58db256bcf2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f58db256bcf2
description:
Merge with the head.
diffstat:
13 files changed, 204 insertions(+), 990 deletions(-)
src/arch/arm/SConscript | 2
src/arch/arm/faults.cc | 534 +--------
src/arch/arm/faults.hh | 565 ----------
src/arch/arm/intregs.hh | 15
src/arch/arm/isa.hh | 8
src/arch/arm/isa/formats/unimp.isa | 2
src/arch/arm/isa/formats/unknown.isa | 2
src/arch/arm/isa_traits.hh | 2
src/arch/arm/miscregs.hh | 37
src/arch/arm/utility.cc | 19
src/arch/x86/isa/insts/general_purpose/data_transfer/move.py | 4
src/arch/x86/isa/microops/mediaop.isa | 2
src/sim/syscall_emul.cc | 2
diffs (truncated from 1480 to 300 lines):
diff -r 48d10ba361c9 -r f58db256bcf2 src/arch/arm/SConscript
--- a/src/arch/arm/SConscript Tue Nov 10 21:10:18 2009 -0800
+++ b/src/arch/arm/SConscript Tue Nov 10 21:12:53 2009 -0800
@@ -48,7 +48,7 @@
SimObject('ArmTLB.py')
TraceFlag('Arm')
-
+ TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
if env['FULL_SYSTEM']:
#Insert Full-System Files Here
pass
diff -r 48d10ba361c9 -r f58db256bcf2 src/arch/arm/faults.cc
--- a/src/arch/arm/faults.cc Tue Nov 10 21:10:18 2009 -0800
+++ b/src/arch/arm/faults.cc Tue Nov 10 21:12:53 2009 -0800
@@ -26,488 +26,114 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Gabe Black
- * Stephen Hines
+ * Authors: Ali Saidi
+ * Gabe Black
*/
#include "arch/arm/faults.hh"
#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include "base/trace.hh"
-#if !FULL_SYSTEM
-#include "sim/process.hh"
-#include "mem/page_table.hh"
-#endif
namespace ArmISA
{
-FaultName MachineCheckFault::_name = "Machine Check";
-FaultVect MachineCheckFault::_vect = 0x0401;
-FaultStat MachineCheckFault::_count;
+template<> ArmFaultBase::FaultVals ArmFault<Reset>::vals =
+ {"reset", 0x00, MODE_SVC, 0, 0, true, true};
-FaultName AlignmentFault::_name = "Alignment";
-FaultVect AlignmentFault::_vect = 0x0301;
-FaultStat AlignmentFault::_count;
+template<> ArmFaultBase::FaultVals ArmFault<UndefinedInstruction>::vals =
+ {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
-FaultName ResetFault::_name = "Reset Fault";
-#if FULL_SYSTEM
-FaultVect ResetFault::_vect = 0xBFC00000;
-#else
-FaultVect ResetFault::_vect = 0x001;
-#endif
-FaultStat ResetFault::_count;
+template<> ArmFaultBase::FaultVals ArmFault<SupervisorCall>::vals =
+ {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
-FaultName AddressErrorFault::_name = "Address Error";
-FaultVect AddressErrorFault::_vect = 0x0180;
-FaultStat AddressErrorFault::_count;
+template<> ArmFaultBase::FaultVals ArmFault<PrefetchAbort>::vals =
+ {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
-FaultName StoreAddressErrorFault::_name = "Store Address Error";
-FaultVect StoreAddressErrorFault::_vect = 0x0180;
-FaultStat StoreAddressErrorFault::_count;
+template<> ArmFaultBase::FaultVals ArmFault<DataAbort>::vals =
+ {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
+template<> ArmFaultBase::FaultVals ArmFault<Interrupt>::vals =
+ {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
-FaultName SystemCallFault::_name = "Syscall";
-FaultVect SystemCallFault::_vect = 0x0180;
-FaultStat SystemCallFault::_count;
+template<> ArmFaultBase::FaultVals ArmFault<FastInterrupt>::vals =
+ {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
-FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable Fault";
-FaultVect CoprocessorUnusableFault::_vect = 0x180;
-FaultStat CoprocessorUnusableFault::_count;
+Addr
+ArmFaultBase::getVector(ThreadContext *tc)
+{
+ // ARM ARM B1-3
-FaultName ReservedInstructionFault::_name = "Reserved Instruction Fault";
-FaultVect ReservedInstructionFault::_vect = 0x0180;
-FaultStat ReservedInstructionFault::_count;
-
-FaultName ThreadFault::_name = "Thread Fault";
-FaultVect ThreadFault::_vect = 0x00F1;
-FaultStat ThreadFault::_count;
-
-
-FaultName ArithmeticFault::_name = "Arithmetic Overflow Exception";
-FaultVect ArithmeticFault::_vect = 0x180;
-FaultStat ArithmeticFault::_count;
-
-FaultName UnimplementedOpcodeFault::_name = "opdec";
-FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
-FaultStat UnimplementedOpcodeFault::_count;
-
-FaultName InterruptFault::_name = "interrupt";
-FaultVect InterruptFault::_vect = 0x0180;
-FaultStat InterruptFault::_count;
-
-FaultName TrapFault::_name = "Trap";
-FaultVect TrapFault::_vect = 0x0180;
-FaultStat TrapFault::_count;
-
-FaultName BreakpointFault::_name = "Breakpoint";
-FaultVect BreakpointFault::_vect = 0x0180;
-FaultStat BreakpointFault::_count;
-
-
-FaultName ItbInvalidFault::_name = "Invalid TLB Entry Exception (I-Fetch/LW)";
-FaultVect ItbInvalidFault::_vect = 0x0180;
-FaultStat ItbInvalidFault::_count;
-
-FaultName ItbPageFault::_name = "itbmiss";
-FaultVect ItbPageFault::_vect = 0x0181;
-FaultStat ItbPageFault::_count;
-
-FaultName ItbMissFault::_name = "itbmiss";
-FaultVect ItbMissFault::_vect = 0x0181;
-FaultStat ItbMissFault::_count;
-
-FaultName ItbAcvFault::_name = "iaccvio";
-FaultVect ItbAcvFault::_vect = 0x0081;
-FaultStat ItbAcvFault::_count;
-
-FaultName ItbRefillFault::_name = "TLB Refill Exception (I-Fetch/LW)";
-FaultVect ItbRefillFault::_vect = 0x0180;
-FaultStat ItbRefillFault::_count;
-
-FaultName NDtbMissFault::_name = "dtb_miss_single";
-FaultVect NDtbMissFault::_vect = 0x0201;
-FaultStat NDtbMissFault::_count;
-
-FaultName PDtbMissFault::_name = "dtb_miss_double";
-FaultVect PDtbMissFault::_vect = 0x0281;
-FaultStat PDtbMissFault::_count;
-
-FaultName DtbPageFault::_name = "dfault";
-FaultVect DtbPageFault::_vect = 0x0381;
-FaultStat DtbPageFault::_count;
-
-FaultName DtbAcvFault::_name = "dfault";
-FaultVect DtbAcvFault::_vect = 0x0381;
-FaultStat DtbAcvFault::_count;
-
-FaultName DtbInvalidFault::_name = "Invalid TLB Entry Exception (Store)";
-FaultVect DtbInvalidFault::_vect = 0x0180;
-FaultStat DtbInvalidFault::_count;
-
-FaultName DtbRefillFault::_name = "TLB Refill Exception (Store)";
-FaultVect DtbRefillFault::_vect = 0x0180;
-FaultStat DtbRefillFault::_count;
-
-FaultName TLBModifiedFault::_name = "TLB Modified Exception";
-FaultVect TLBModifiedFault::_vect = 0x0180;
-FaultStat TLBModifiedFault::_count;
-
-FaultName FloatEnableFault::_name = "float_enable_fault";
-FaultVect FloatEnableFault::_vect = 0x0581;
-FaultStat FloatEnableFault::_count;
-
-FaultName IntegerOverflowFault::_name = "Integer Overflow Fault";
-FaultVect IntegerOverflowFault::_vect = 0x0501;
-FaultStat IntegerOverflowFault::_count;
-
-FaultName DspStateDisabledFault::_name = "DSP Disabled Fault";
-FaultVect DspStateDisabledFault::_vect = 0x001a;
-FaultStat DspStateDisabledFault::_count;
-
-#if FULL_SYSTEM
-void ArmFault::setHandlerPC(Addr HandlerBase, ThreadContext *tc)
-{
- tc->setPC(HandlerBase);
- tc->setNextPC(HandlerBase+sizeof(MachInst));
- tc->setNextNPC(HandlerBase+2*sizeof(MachInst));
-}
-
-void ArmFault::setExceptionState(ThreadContext *tc,uint8_t ExcCode)
-{
- // modify SRS Ctl - Save CSS, put ESS into CSS
- MiscReg stat = tc->readMiscReg(ArmISA::Status);
- if(bits(stat,Status_EXL) != 1 && bits(stat,Status_BEV) != 1)
- {
- // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
- MiscReg srs = tc->readMiscReg(ArmISA::SRSCtl);
- uint8_t CSS,ESS;
- CSS = bits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO);
- ESS = bits(srs,SRSCtl_ESS_HI,SRSCtl_ESS_LO);
- // Move CSS to PSS
- replaceBits(srs,SRSCtl_PSS_HI,SRSCtl_PSS_LO,CSS);
- // Move ESS to CSS
- replaceBits(srs,SRSCtl_CSS_HI,SRSCtl_CSS_LO,ESS);
- tc->setMiscRegNoEffect(ArmISA::SRSCtl,srs);
- //tc->setShadowSet(ESS);
- }
-
- // set EXL bit (don't care if it is already set!)
- replaceBits(stat,Status_EXL_HI,Status_EXL_LO,1);
- tc->setMiscRegNoEffect(ArmISA::Status,stat);
-
- // write EPC
- // warn("Set EPC to %x\n",tc->readPC());
- // CHECK ME or FIXME or FIX ME or POSSIBLE HACK
- // Check to see if the exception occurred in the branch delay slot
- DPRINTF(Arm,"PC: %x, NextPC: %x, NNPC:
%x\n",tc->readPC(),tc->readNextPC(),tc->readNextNPC());
- int C_BD=0;
- if(tc->readPC() + sizeof(MachInst) != tc->readNextPC()){
- tc->setMiscRegNoEffect(ArmISA::EPC,tc->readPC()-sizeof(MachInst));
- // In the branch delay slot? set CAUSE_31
- C_BD = 1;
- } else {
- tc->setMiscRegNoEffect(ArmISA::EPC,tc->readPC());
- // In the branch delay slot? reset CAUSE_31
- C_BD = 0;
- }
-
- // Set Cause_EXCCODE field
- MiscReg cause = tc->readMiscReg(ArmISA::Cause);
- replaceBits(cause,Cause_EXCCODE_HI,Cause_EXCCODE_LO,ExcCode);
- replaceBits(cause,Cause_BD_HI,Cause_BD_LO,C_BD);
- replaceBits(cause,Cause_CE_HI,Cause_CE_LO,0);
- tc->setMiscRegNoEffect(ArmISA::Cause,cause);
+ SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
+
+ // panic if SCTLR.VE because I have no idea what to do with vectored
+ // interrupts
+ assert(!sctlr.ve);
+
+ if (!sctlr.v)
+ return offset();
+ return offset() + HighVecs;
}
-void ArithmeticFault::invoke(ThreadContext *tc)
+#if FULL_SYSTEM
+
+void
+ArmFaultBase::invoke(ThreadContext *tc)
{
- DPRINTF(Arm,"%s encountered.\n", name());
- setExceptionState(tc,0xC);
+ // ARM ARM B1.6.3
+ FaultBase::invoke(tc);
+ countStat()++;
- // Set new PC
- Addr HandlerBase;
- MiscReg stat = tc->readMiscReg(ArmISA::Status);
- // Here, the handler is dependent on BEV, which is not modified by
setExceptionState()
- if(bits(stat,Status_BEV)==0){ // See MIPS ARM Vol 3, Revision 2, Page 38
- HandlerBase= vect() + tc->readMiscReg(ArmISA::EBase);
- }else{
- HandlerBase = 0xBFC00200;
- }
- setHandlerPC(HandlerBase,tc);
- // warn("Exception Handler At: %x \n",HandlerBase);
+ SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
+ CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+ CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
+ tc->readIntReg(INTREG_CONDCODES);
+
+
+ cpsr.mode = nextMode();
+ cpsr.it1 = cpsr.it2 = 0;
+ cpsr.j = 0;
+
+ if (sctlr.te)
+ cpsr.t = 1;
+ cpsr.a = cpsr.a | abortDisable();
+ cpsr.f = cpsr.f | fiqDisable();
+ cpsr.i = 1;
+ tc->setMiscReg(MISCREG_CPSR, cpsr);
+ tc->setIntReg(INTREG_LR, tc->readPC() +
+ (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
+
+ switch (nextMode()) {
+ case MODE_FIQ:
+ tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
+ break;
+ case MODE_IRQ:
+ tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
+ break;
+ case MODE_SVC:
+ tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
+ break;
+ case MODE_UNDEFINED:
+ tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
+ break;
+ case MODE_ABORT:
+ tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
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