changeset 33ac9df63f3e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=33ac9df63f3e
description:
ARM: Define a mask to differentiate purely CPSR bits from CondCodes
bits.
diffstat:
1 file changed, 4 insertions(+)
src/arch/arm/miscregs.hh | 4 ++++
diffs (14 lines):
diff -r ac658ad78659 -r 33ac9df63f3e src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh Sat Nov 14 19:22:30 2009 -0800
+++ b/src/arch/arm/miscregs.hh Sat Nov 14 19:22:30 2009 -0800
@@ -93,6 +93,10 @@
Bitfield<4, 0> mode;
EndBitUnion(CPSR)
+ // This mask selects bits of the CPSR that actually go in the CondCodes
+ // integer register to allow renaming.
+ static const uint32_t CondCodesMask = 0xF80F0000;
+
BitUnion32(SCTLR)
Bitfield<30> te; // Thumb Exception Enable
Bitfield<29> afe; // Access flag enable
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