changeset 065d296b929b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=065d296b929b
description:
ARM: Fix up the implmentation of the msr instruction.
diffstat:
1 file changed, 27 insertions(+), 10 deletions(-)
src/arch/arm/isa/decoder.isa | 37 +++++++++++++++++++++++++++----------
diffs (48 lines):
diff -r 33ac9df63f3e -r 065d296b929b src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Sat Nov 14 19:22:30 2009 -0800
+++ b/src/arch/arm/isa/decoder.isa Sat Nov 14 19:22:30 2009 -0800
@@ -113,17 +113,34 @@
0x8: PredOp::mrs_cpsr({{
Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
}});
- 0x9: PredOp::msr_cpsr({{
- //assert(!RN<1:0>);
- if (OPCODE_18) {
- Cpsr = Cpsr<31:20> | mbits(Rm, 19, 16) |
Cpsr<15:0>;
- }
- if (OPCODE_19) {
- CondCodes = mbits(Rm, 31,27);
- }
- }});
+ 0x9: decode USEIMM {
+ // The mask field is the same as the RN index.
+ 0: PredImmOp::msr_cpsr_imm({{
+ uint32_t newCpsr =
+ cpsrWriteByInstr(Cpsr | CondCodes,
+ rotated_imm, RN, false);
+ Cpsr = ~CondCodesMask & newCpsr;
+ CondCodes = CondCodesMask & newCpsr;
+ }});
+ 1: PredOp::msr_cpsr_reg({{
+ uint32_t newCpsr =
+ cpsrWriteByInstr(Cpsr | CondCodes,
+ Rm, RN, false);
+ Cpsr = ~CondCodesMask & newCpsr;
+ CondCodes = CondCodesMask & newCpsr;
+ }});
+ }
0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
- 0xb: WarnUnimpl::msr_spsr();
+ 0xb: decode USEIMM {
+ // The mask field is the same as the RN index.
+ 0: PredImmOp::msr_spsr_imm({{
+ Spsr = spsrWriteByInstr(Spsr, rotated_imm,
+ RN, false);
+ }});
+ 1: PredOp::msr_spsr_reg({{
+ Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
+ }});
+ }
}
0x1: decode OPCODE {
0x9: BranchExchange::bx({{ }});
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