changeset 81220645c196 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=81220645c196
description:
imported patch isa_fixes2.diff
diffstat:
1 file changed, 19 insertions(+), 11 deletions(-)
src/arch/arm/isa/decoder.isa | 30 +++++++++++++++++++-----------
diffs (41 lines):
diff -r e9970c1bccdd -r 81220645c196 src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Sun Nov 15 00:23:14 2009 -0800
+++ b/src/arch/arm/isa/decoder.isa Mon Nov 16 11:37:03 2009 -0600
@@ -221,18 +221,26 @@
1: decode OPCODE {
// The following two instructions aren't supposed to be defined
0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
- 0x9: DataImmOp::msr_ia_cpsr ({{
- //assert(!RN<1:0>);
- if (OPCODE_18) {
- Cpsr = Cpsr<31:20> | rotated_imm | Cpsr<15:0>;
- }
- if (OPCODE_19) {
- CondCodes = rotated_imm;
- }
+ 0x9: decode RN {
+ 0: decode IMM {
+ 0: PredImmOp::nop({{ ; }});
+ 1: WarnUnimpl::yield();
+ 2: WarnUnimpl::wfe();
+ 3: WarnUnimpl::wfi();
+ 4: WarnUnimpl::sev();
+ }
+ default: PredImmOp::msr_i_cpsr({{
+ uint32_t newCpsr =
+ cpsrWriteByInstr(Cpsr | CondCodes,
+ rotated_imm, RN, false);
+ Cpsr = ~CondCodesMask & newCpsr;
+ CondCodes = CondCodesMask & newCpsr;
+ }});
+ }
+ 0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>;
}});
+ 0xb: PredImmOp::msr_i_spsr({{
+ Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
}});
-
- 0xa: WarnUnimpl::mrs_i_cpsr();
- 0xb: WarnUnimpl::mrs_i_spsr();
}
}
0x2: AddrMode2::addrMode2(Disp, disp);
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