# HG changeset patch
# User Ali Saidi <[email protected]>
# Date 1258398516 21600
# Node ID 4fbeb3ff43d35580a375defac4e4ae80181e541a
# Parent 81220645c1967b05e76f6273d57543b2f5eb7b85
ARM: Boilerplate full-system code.
diff --git a/build_opts/ARM_FS b/build_opts/ARM_FS
new file mode 100644
--- /dev/null
+++ b/build_opts/ARM_FS
@@ -0,0 +1,3 @@
+TARGET_ISA = 'arm'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
+FULL_SYSTEM = 1
diff --git a/src/arch/arm/ArmInterrupts.py b/src/arch/arm/ArmInterrupts.py
new file mode 100644
--- /dev/null
+++ b/src/arch/arm/ArmInterrupts.py
@@ -0,0 +1,33 @@
+# Copyright (c) 2009 ARM Limited
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+
+from m5.SimObject import SimObject
+
+class ArmInterrupts(SimObject):
+ type = 'ArmInterrupts'
+ cxx_class = 'ArmISA::Interrupts'
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
new file mode 100644
--- /dev/null
+++ b/src/arch/arm/ArmSystem.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2009 ARM Limited
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+
+from m5.params import *
+
+from System import System
+
+class ArmSystem(System):
+ type = 'ArmSystem'
+
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -1,6 +1,7 @@
# -*- mode:python -*-
# Copyright (c) 2007-2008 The Florida State University
+# Copyright (c) 2009 ARM Limited
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -27,6 +28,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Stephen Hines
+# Ali Saidi
Import('*')
@@ -43,6 +45,7 @@
Source('pagetable.cc')
Source('tlb.cc')
Source('vtophys.cc')
+ Source('utility.cc')
SimObject('ArmNativeTrace.py')
SimObject('ArmTLB.py')
@@ -50,8 +53,12 @@
TraceFlag('Arm')
TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
if env['FULL_SYSTEM']:
- #Insert Full-System Files Here
- pass
+ Source('interrupts.cc')
+ Source('stacktrace.cc')
+ Source('system.cc')
+
+ SimObject('ArmInterrupts.py')
+ SimObject('ArmSystem.py')
else:
Source('process.cc')
Source('linux/linux.cc')
diff --git a/src/arch/arm/interrupts.cc b/src/arch/arm/interrupts.cc
new file mode 100644
--- /dev/null
+++ b/src/arch/arm/interrupts.cc
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2009 ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include "arch/arm/interrupts.hh"
+
+ArmISA::Interrupts *
+ArmInterruptsParams::create()
+{
+ return new ArmISA::Interrupts(this);
+}
diff --git a/src/arch/sparc/interrupts.hh b/src/arch/arm/interrupts.hh
copy from src/arch/sparc/interrupts.hh
copy to src/arch/arm/interrupts.hh
--- a/src/arch/sparc/interrupts.hh
+++ b/src/arch/arm/interrupts.hh
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2009 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,20 +27,19 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ali Saidi
- * Lisa Hsu
*/
-#ifndef __ARCH_SPARC_INTERRUPT_HH__
-#define __ARCH_SPARC_INTERRUPT_HH__
+#ifndef __ARCH_ARM_INTERRUPT_HH__
+#define __ARCH_ARM_INTERRUPT_HH__
-#include "arch/sparc/faults.hh"
-#include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/registers.hh"
+#include "arch/arm/faults.hh"
+#include "arch/arm/isa_traits.hh"
+#include "arch/arm/registers.hh"
#include "cpu/thread_context.hh"
-#include "params/SparcInterrupts.hh"
+#include "params/ArmInterrupts.hh"
#include "sim/sim_object.hh"
-namespace SparcISA
+namespace ArmISA
{
class Interrupts : public SimObject
@@ -47,7 +47,6 @@
private:
BaseCPU * cpu;
- uint64_t interrupts[NumInterruptTypes];
uint64_t intStatus;
public:
@@ -58,7 +57,7 @@
cpu = _cpu;
}
- typedef SparcInterruptsParams Params;
+ typedef ArmInterruptsParams Params;
const Params *
params() const
@@ -71,49 +70,20 @@
clearAll();
}
- int
- InterruptLevel(uint64_t softint)
- {
- if (softint & 0x10000 || softint & 0x1)
- return 14;
-
- int level = 15;
- while (level > 0 && !(1 << level & softint))
- level--;
- if (1 << level & softint)
- return level;
- return 0;
- }
void
post(int int_num, int index)
{
- DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
- assert(int_num >= 0 && int_num < NumInterruptTypes);
- assert(index >= 0 && index < 64);
-
- interrupts[int_num] |= ULL(1) << index;
- intStatus |= ULL(1) << int_num;
}
void
clear(int int_num, int index)
{
- DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
- assert(int_num >= 0 && int_num < NumInterruptTypes);
- assert(index >= 0 && index < 64);
-
- interrupts[int_num] &= ~(ULL(1) << index);
- if (!interrupts[int_num])
- intStatus &= ~(ULL(1) << int_num);
}
void
clearAll()
{
- for (int i = 0; i < NumInterruptTypes; ++i) {
- interrupts[i] = 0;
- }
intStatus = 0;
}
@@ -126,56 +96,7 @@
Fault
getInterrupt(ThreadContext *tc)
{
- int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
- int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
- bool ie = pstate & PSTATE::ie;
-
- // THESE ARE IN ORDER OF PRIORITY
- // since there are early returns, and the highest
- // priority interrupts should get serviced,
- // it is v. important that new interrupts are inserted
- // in the right order of processing
- if (hpstate & HPSTATE::hpriv) {
- if (ie) {
- if (interrupts[IT_HINTP]) {
- // This will be cleaned by a HINTP write
- return new HstickMatch;
- }
- if (interrupts[IT_INT_VEC]) {
- // this will be cleared by an ASI read (or write)
- return new InterruptVector;
- }
- }
- } else {
- if (interrupts[IT_TRAP_LEVEL_ZERO]) {
- // this is cleared by deasserting HPSTATE::tlz
- return new TrapLevelZero;
- }
- // HStick matches always happen in priv mode (ie doesn't matter)
- if (interrupts[IT_HINTP]) {
- return new HstickMatch;
- }
- if (interrupts[IT_INT_VEC]) {
- // this will be cleared by an ASI read (or write)
- return new InterruptVector;
- }
- if (ie) {
- if (interrupts[IT_CPU_MONDO]) {
- return new CpuMondo;
- }
- if (interrupts[IT_DEV_MONDO]) {
- return new DevMondo;
- }
- if (interrupts[IT_SOFT_INT]) {
- int level = InterruptLevel(interrupts[IT_SOFT_INT]);
- return new InterruptLevelN(level);
- }
-
- if (interrupts[IT_RES_ERROR]) {
- return new ResumableError;
- }
- } // !hpriv && ie
- } // !hpriv
+ warn_once("ARM Interrupts not handled\n");
return NoFault;
}
@@ -185,27 +106,16 @@
}
- uint64_t
- get_vec(int int_num)
- {
- assert(int_num >= 0 && int_num < NumInterruptTypes);
- return interrupts[int_num];
- }
-
void
serialize(std::ostream &os)
{
- SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
- SERIALIZE_SCALAR(intStatus);
}
void
unserialize(Checkpoint *cp, const std::string §ion)
{
- UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
- UNSERIALIZE_SCALAR(intStatus);
}
};
-} // namespace SPARC_ISA
+} // namespace ARM_ISA
-#endif // __ARCH_SPARC_INTERRUPT_HH__
+#endif // __ARCH_ARM_INTERRUPT_HH__
diff --git a/src/arch/sparc/kernel_stats.hh b/src/arch/arm/kernel_stats.hh
copy from src/arch/sparc/kernel_stats.hh
copy to src/arch/arm/kernel_stats.hh
--- a/src/arch/sparc/kernel_stats.hh
+++ b/src/arch/arm/kernel_stats.hh
@@ -28,8 +28,8 @@
* Authors: Gabe Black
*/
-#ifndef __ARCH_SPARC_KERNEL_STATS_HH__
-#define __ARCH_SPARC_KERNEL_STATS_HH__
+#ifndef __ARCH_ARM_KERNEL_STATS_HH__
+#define __ARCH_ARM_KERNEL_STATS_HH__
#include <map>
#include <stack>
@@ -38,7 +38,7 @@
#include "kern/kernel_stats.hh"
-namespace SparcISA {
+namespace ArmISA {
namespace Kernel {
enum cpu_mode { hypervisor, kernel, user, idle, cpu_mode_num };
@@ -51,7 +51,7 @@
{}
};
-} /* end namespace AlphaISA::Kernel */
-} /* end namespace AlphaISA */
+} /* end namespace ArmISA::Kernel */
+} /* end namespace ArmISA */
-#endif // __ARCH_SPARC_KERNEL_STATS_HH__
+#endif // __ARCH_ARM_KERNEL_STATS_HH__
diff --git a/src/arch/sparc/stacktrace.cc b/src/arch/arm/stacktrace.cc
copy from src/arch/sparc/stacktrace.cc
copy to src/arch/arm/stacktrace.cc
--- a/src/arch/sparc/stacktrace.cc
+++ b/src/arch/arm/stacktrace.cc
@@ -30,9 +30,9 @@
#include <string>
-#include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/stacktrace.hh"
-#include "arch/sparc/vtophys.hh"
+#include "arch/arm/isa_traits.hh"
+#include "arch/arm/stacktrace.hh"
+#include "arch/arm/vtophys.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
@@ -40,7 +40,7 @@
#include "sim/system.hh"
using namespace std;
-namespace SparcISA
+namespace ArmISA
{
ProcessInfo::ProcessInfo(ThreadContext *_tc)
: tc(_tc)
@@ -75,50 +75,19 @@
Addr
ProcessInfo::task(Addr ksp) const
{
- Addr base = ksp & ~0x3fff;
- if (base == ULL(0xfffffc0000000000))
- return 0;
-
- Addr tsk;
-
- VirtualPort *vp;
-
- vp = tc->getVirtPort();
- tsk = vp->readGtoH<Addr>(base + task_off);
-
- return tsk;
+ return 0;
}
int
ProcessInfo::pid(Addr ksp) const
{
- Addr task = this->task(ksp);
- if (!task)
- return -1;
-
- uint16_t pd;
-
- VirtualPort *vp;
-
- vp = tc->getVirtPort();
- pd = vp->readGtoH<uint16_t>(task + pid_off);
-
- return pd;
+ return -1;
}
string
ProcessInfo::name(Addr ksp) const
{
- Addr task = this->task(ksp);
- if (!task)
- return "console";
-
- char comm[256];
- CopyStringOut(tc, comm, task + name_off, sizeof(comm));
- if (!comm[0])
- return "startup";
-
- return comm;
+ return "Implement me";
}
StackTrace::StackTrace()
@@ -139,169 +108,24 @@
void
StackTrace::trace(ThreadContext *_tc, bool is_call)
{
-#if 0
- tc = _tc;
-
- bool usermode = (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18)
!= 0;
-
- Addr pc = tc->readNextPC();
- bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
- pc <= tc->getSystemPtr()->kernelEnd;
-
- if (usermode) {
- stack.push_back(user);
- return;
- }
-
- if (!kernel) {
- stack.push_back(console);
- return;
- }
-
- SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
- Addr ksp = tc->readIntReg(SparcISA::StackPointerReg);
- Addr bottom = ksp & ~0x3fff;
- Addr addr;
-
- if (is_call) {
- if (!symtab->findNearestAddr(pc, addr))
- panic("could not find address %#x", pc);
-
- stack.push_back(addr);
- pc = tc->readPC();
- }
-
- Addr ra;
- int size;
-
- while (ksp > bottom) {
- if (!symtab->findNearestAddr(pc, addr))
- panic("could not find symbol for pc=%#x", pc);
- assert(pc >= addr && "symbol botch: callpc < func");
-
- stack.push_back(addr);
-
- if (isEntry(addr))
- return;
-
- if (decodePrologue(ksp, pc, addr, size, ra)) {
- if (!ra)
- return;
-
- if (size <= 0) {
- stack.push_back(unknown);
- return;
- }
-
- pc = ra;
- ksp += size;
- } else {
- stack.push_back(unknown);
- return;
- }
-
- bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
- pc <= tc->getSystemPtr()->kernelEnd;
- if (!kernel)
- return;
-
- if (stack.size() >= 1000)
- panic("unwinding too far");
- }
-
- panic("unwinding too far");
-#endif
}
bool
StackTrace::isEntry(Addr addr)
{
-#if 0
- if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp12))
- return true;
-
- if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp7))
- return true;
-
- if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp11))
- return true;
-
- if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp21))
- return true;
-
- if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp9))
- return true;
-
- if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp2))
- return true;
-#endif
return false;
}
bool
StackTrace::decodeStack(MachInst inst, int &disp)
{
- // lda $sp, -disp($sp)
- //
- // Opcode<31:26> == 0x08
- // RA<25:21> == 30
- // RB<20:16> == 30
- // Disp<15:0>
- const MachInst mem_mask = 0xffff0000;
- const MachInst lda_pattern = 0x23de0000;
- const MachInst lda_disp_mask = 0x0000ffff;
-
- // subq $sp, disp, $sp
- // addq $sp, disp, $sp
- //
- // Opcode<31:26> == 0x10
- // RA<25:21> == 30
- // Lit<20:13>
- // One<12> = 1
- // Func<11:5> == 0x20 (addq)
- // Func<11:5> == 0x29 (subq)
- // RC<4:0> == 30
- const MachInst intop_mask = 0xffe01fff;
- const MachInst addq_pattern = 0x43c0141e;
- const MachInst subq_pattern = 0x43c0153e;
- const MachInst intop_disp_mask = 0x001fe000;
- const int intop_disp_shift = 13;
-
- if ((inst & mem_mask) == lda_pattern)
- disp = -sext<16>(inst & lda_disp_mask);
- else if ((inst & intop_mask) == addq_pattern)
- disp = -int((inst & intop_disp_mask) >> intop_disp_shift);
- else if ((inst & intop_mask) == subq_pattern)
- disp = int((inst & intop_disp_mask) >> intop_disp_shift);
- else
- return false;
-
- return true;
+ return false;
}
bool
StackTrace::decodeSave(MachInst inst, int ®, int &disp)
{
- // lda $stq, disp($sp)
- //
- // Opcode<31:26> == 0x08
- // RA<25:21> == ?
- // RB<20:16> == 30
- // Disp<15:0>
- const MachInst stq_mask = 0xfc1f0000;
- const MachInst stq_pattern = 0xb41e0000;
- const MachInst stq_disp_mask = 0x0000ffff;
- const MachInst reg_mask = 0x03e00000;
- const int reg_shift = 21;
-
- if ((inst & stq_mask) == stq_pattern) {
- reg = (inst & reg_mask) >> reg_shift;
- disp = sext<16>(inst & stq_disp_mask);
- } else {
- return false;
- }
-
- return true;
+ return false;
}
/*
@@ -312,57 +136,16 @@
StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
int &size, Addr &ra)
{
- size = 0;
- ra = 0;
-
- for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
- MachInst inst;
- CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst));
-
- int reg, disp;
- if (decodeStack(inst, disp)) {
- if (size) {
- // panic("decoding frame size again");
- return true;
- }
- size += disp;
- } else if (decodeSave(inst, reg, disp)) {
- if (!ra && reg == ReturnAddressReg) {
- CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
- if (!ra) {
- // panic("no return address value pc=%#x\n", pc);
- return false;
- }
- }
- }
- }
-
- return true;
+ return false;
}
#if TRACING_ON
void
StackTrace::dump()
{
- StringWrap name(tc->getCpuPtr()->name());
- SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
-
DPRINTFN("------ Stack ------\n");
-
- string symbol;
- for (int i = 0, size = stack.size(); i < size; ++i) {
- Addr addr = stack[size - i - 1];
- if (addr == user)
- symbol = "user";
- else if (addr == console)
- symbol = "console";
- else if (addr == unknown)
- symbol = "unknown";
- else
- symtab->findSymbol(addr, symbol);
-
- DPRINTFN("%#x: %s\n", addr, symbol);
- }
+
+ DPRINTFN(" Not implemented\n");
}
#endif
}
diff --git a/src/arch/arm/stacktrace.hh b/src/arch/arm/stacktrace.hh
--- a/src/arch/arm/stacktrace.hh
+++ b/src/arch/arm/stacktrace.hh
@@ -1,6 +1,5 @@
/*
* Copyright (c) 2005 The Regents of The University of Michigan
- * Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,23 +25,21 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Ali Saidi
- * Stephen Hines
+ * Authors: Nathan Binkert
*/
#ifndef __ARCH_ARM_STACKTRACE_HH__
#define __ARCH_ARM_STACKTRACE_HH__
#include "base/trace.hh"
-#include "config/the_isa.hh"
#include "cpu/static_inst.hh"
class ThreadContext;
-class StackTrace;
-
namespace ArmISA
{
+class StackTrace;
+
class ProcessInfo
{
private:
@@ -65,7 +62,7 @@
class StackTrace
{
protected:
- typedef TheISA::MachInst MachInst;
+ typedef ArmISA::MachInst MachInst;
private:
ThreadContext *tc;
std::vector<Addr> stack;
@@ -95,10 +92,6 @@
public:
const std::vector<Addr> &getstack() const { return stack; }
- static const int user = 1;
- static const int console = 2;
- static const int unknown = 3;
-
#if TRACING_ON
private:
void dump();
@@ -124,6 +117,6 @@
return true;
}
-}
+} // Namespace ArmISA
#endif // __ARCH_ARM_STACKTRACE_HH__
diff --git a/src/arch/sparc/system.cc b/src/arch/arm/system.cc
copy from src/arch/sparc/system.cc
copy to src/arch/arm/system.cc
--- a/src/arch/sparc/system.cc
+++ b/src/arch/arm/system.cc
@@ -28,196 +28,24 @@
* Authors: Ali Saidi
*/
-#include "arch/sparc/system.hh"
-#include "arch/vtophys.hh"
-#include "base/remote_gdb.hh"
-#include "base/loader/object_file.hh"
-#include "base/loader/symtab.hh"
-#include "base/trace.hh"
-#include "mem/physical.hh"
-#include "params/SparcSystem.hh"
-#include "sim/byteswap.hh"
+#include "arch/arm/system.hh"
-using namespace BigEndianGuest;
+using namespace LittleEndianGuest;
-SparcSystem::SparcSystem(Params *p)
- : System(p), sysTick(0),funcRomPort(p->name + "-fromport"),
- funcNvramPort(p->name + "-fnvramport"),
- funcHypDescPort(p->name + "-fhypdescport"),
- funcPartDescPort(p->name + "-fpartdescport")
+ArmSystem::ArmSystem(Params *p)
+ : System(p)
{
- resetSymtab = new SymbolTable;
- hypervisorSymtab = new SymbolTable;
- openbootSymtab = new SymbolTable;
- nvramSymtab = new SymbolTable;
- hypervisorDescSymtab = new SymbolTable;
- partitionDescSymtab = new SymbolTable;
-
- Port *rom_port;
- rom_port = params()->rom->getPort("functional");
- funcRomPort.setPeer(rom_port);
- rom_port->setPeer(&funcRomPort);
-
- rom_port = params()->nvram->getPort("functional");
- funcNvramPort.setPeer(rom_port);
- rom_port->setPeer(&funcNvramPort);
-
- rom_port = params()->hypervisor_desc->getPort("functional");
- funcHypDescPort.setPeer(rom_port);
- rom_port->setPeer(&funcHypDescPort);
-
- rom_port = params()->partition_desc->getPort("functional");
- funcPartDescPort.setPeer(rom_port);
- rom_port->setPeer(&funcPartDescPort);
-
- /**
- * Load the boot code, and hypervisor into memory.
- */
- // Read the reset binary
- reset = createObjectFile(params()->reset_bin, true);
- if (reset == NULL)
- fatal("Could not load reset binary %s", params()->reset_bin);
-
- // Read the openboot binary
- openboot = createObjectFile(params()->openboot_bin, true);
- if (openboot == NULL)
- fatal("Could not load openboot bianry %s", params()->openboot_bin);
-
- // Read the hypervisor binary
- hypervisor = createObjectFile(params()->hypervisor_bin, true);
- if (hypervisor == NULL)
- fatal("Could not load hypervisor binary %s", params()->hypervisor_bin);
-
- // Read the nvram image
- nvram = createObjectFile(params()->nvram_bin, true);
- if (nvram == NULL)
- fatal("Could not load nvram image %s", params()->nvram_bin);
-
- // Read the hypervisor description image
- hypervisor_desc = createObjectFile(params()->hypervisor_desc_bin, true);
- if (hypervisor_desc == NULL)
- fatal("Could not load hypervisor description image %s",
- params()->hypervisor_desc_bin);
-
- // Read the partition description image
- partition_desc = createObjectFile(params()->partition_desc_bin, true);
- if (partition_desc == NULL)
- fatal("Could not load partition description image %s",
- params()->partition_desc_bin);
-
-
- // Load reset binary into memory
- reset->setTextBase(params()->reset_addr);
- reset->loadSections(&funcRomPort);
- // Load the openboot binary
- openboot->setTextBase(params()->openboot_addr);
- openboot->loadSections(&funcRomPort);
- // Load the hypervisor binary
- hypervisor->setTextBase(params()->hypervisor_addr);
- hypervisor->loadSections(&funcRomPort);
- // Load the nvram image
- nvram->setTextBase(params()->nvram_addr);
- nvram->loadSections(&funcNvramPort);
- // Load the hypervisor description image
- hypervisor_desc->setTextBase(params()->hypervisor_desc_addr);
- hypervisor_desc->loadSections(&funcHypDescPort);
- // Load the partition description image
- partition_desc->setTextBase(params()->partition_desc_addr);
- partition_desc->loadSections(&funcPartDescPort);
-
- // load symbols
- if (!reset->loadGlobalSymbols(resetSymtab))
- panic("could not load reset symbols\n");
-
- if (!openboot->loadGlobalSymbols(openbootSymtab))
- panic("could not load openboot symbols\n");
-
- if (!hypervisor->loadLocalSymbols(hypervisorSymtab))
- panic("could not load hypervisor symbols\n");
-
- if (!nvram->loadLocalSymbols(nvramSymtab))
- panic("could not load nvram symbols\n");
-
- if (!hypervisor_desc->loadLocalSymbols(hypervisorDescSymtab))
- panic("could not load hypervisor description symbols\n");
-
- if (!partition_desc->loadLocalSymbols(partitionDescSymtab))
- panic("could not load partition description symbols\n");
-
- // load symbols into debug table
- if (!reset->loadGlobalSymbols(debugSymbolTable))
- panic("could not load reset symbols\n");
-
- if (!openboot->loadGlobalSymbols(debugSymbolTable))
- panic("could not load openboot symbols\n");
-
- if (!hypervisor->loadLocalSymbols(debugSymbolTable))
- panic("could not load hypervisor symbols\n");
-
- // Strip off the rom address so when the hypervisor is copied into memory
we
- // have symbols still
- if (!hypervisor->loadLocalSymbols(debugSymbolTable, 0xFFFFFF))
- panic("could not load hypervisor symbols\n");
-
- if (!nvram->loadGlobalSymbols(debugSymbolTable))
- panic("could not load reset symbols\n");
-
- if (!hypervisor_desc->loadGlobalSymbols(debugSymbolTable))
- panic("could not load hypervisor description symbols\n");
-
- if (!partition_desc->loadLocalSymbols(debugSymbolTable))
- panic("could not load partition description symbols\n");
-
-
- // @todo any fixup code over writing data in binaries on setting break
- // events on functions should happen here.
}
-SparcSystem::~SparcSystem()
+ArmSystem::~ArmSystem()
{
- delete resetSymtab;
- delete hypervisorSymtab;
- delete openbootSymtab;
- delete nvramSymtab;
- delete hypervisorDescSymtab;
- delete partitionDescSymtab;
- delete reset;
- delete openboot;
- delete hypervisor;
- delete nvram;
- delete hypervisor_desc;
- delete partition_desc;
}
-void
-SparcSystem::serialize(std::ostream &os)
+
+ArmSystem *
+ArmSystemParams::create()
{
- System::serialize(os);
- resetSymtab->serialize("reset_symtab", os);
- hypervisorSymtab->serialize("hypervisor_symtab", os);
- openbootSymtab->serialize("openboot_symtab", os);
- nvramSymtab->serialize("nvram_symtab", os);
- hypervisorDescSymtab->serialize("hypervisor_desc_symtab", os);
- partitionDescSymtab->serialize("partition_desc_symtab", os);
+ return new ArmSystem(this);
}
-
-
-void
-SparcSystem::unserialize(Checkpoint *cp, const std::string §ion)
-{
- System::unserialize(cp,section);
- resetSymtab->unserialize("reset_symtab", cp, section);
- hypervisorSymtab->unserialize("hypervisor_symtab", cp, section);
- openbootSymtab->unserialize("openboot_symtab", cp, section);
- nvramSymtab->unserialize("nvram_symtab", cp, section);
- hypervisorDescSymtab->unserialize("hypervisor_desc_symtab", cp, section);
- partitionDescSymtab->unserialize("partition_desc_symtab", cp, section);
-}
-
-SparcSystem *
-SparcSystemParams::create()
-{
- return new SparcSystem(this);
-}
diff --git a/src/arch/sparc/system.hh b/src/arch/arm/system.hh
copy from src/arch/sparc/system.hh
copy to src/arch/arm/system.hh
--- a/src/arch/sparc/system.hh
+++ b/src/arch/arm/system.hh
@@ -28,108 +28,23 @@
* Authors: Ali Saidi
*/
-#ifndef __ARCH_SPARC_SYSTEM_HH__
-#define __ARCH_SPARC_SYSTEM_HH__
+#ifndef __ARCH_ARM_SYSTEM_HH__
+#define __ARCH_ARM_SYSTEM_HH__
#include <string>
#include <vector>
-#include "base/loader/symtab.hh"
-#include "cpu/pc_event.hh"
-#include "kern/system_events.hh"
-#include "params/SparcSystem.hh"
+#include "params/ArmSystem.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
-class SparcSystem : public System
+class ArmSystem : public System
{
public:
- typedef SparcSystemParams Params;
- SparcSystem(Params *p);
- ~SparcSystem();
-
-/**
- * Serialization stuff
- */
- public:
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string §ion);
-
- /** reset binary symbol table */
- SymbolTable *resetSymtab;
-
- /** hypervison binary symbol table */
- SymbolTable *hypervisorSymtab;
-
- /** openboot symbol table */
- SymbolTable *openbootSymtab;
-
- /** nvram symbol table? */
- SymbolTable *nvramSymtab;
-
- /** hypervisor desc symbol table? */
- SymbolTable *hypervisorDescSymtab;
-
- /** partition desc symbol table? */
- SymbolTable *partitionDescSymtab;
-
- /** Object pointer for the reset binary */
- ObjectFile *reset;
-
- /** Object pointer for the hypervisor code */
- ObjectFile *hypervisor;
-
- /** Object pointer for the openboot code */
- ObjectFile *openboot;
-
- /** Object pointer for the nvram image */
- ObjectFile *nvram;
-
- /** Object pointer for the hypervisor description image */
- ObjectFile *hypervisor_desc;
-
- /** Object pointer for the partition description image */
- ObjectFile *partition_desc;
-
- /** System Tick for syncronized tick across all cpus. */
- Tick sysTick;
-
- /** functional port to ROM */
- FunctionalPort funcRomPort;
-
- /** functional port to nvram */
- FunctionalPort funcNvramPort;
-
- /** functional port to hypervisor description */
- FunctionalPort funcHypDescPort;
-
- /** functional port to partition description */
- FunctionalPort funcPartDescPort;
-
- protected:
- const Params *params() const { return (const Params *)_params; }
-
- /** Add a function-based event to reset binary. */
- template <class T>
- T *addResetFuncEvent(const char *lbl)
- {
- return addFuncEvent<T>(resetSymtab, lbl);
- }
-
- /** Add a function-based event to the hypervisor. */
- template <class T>
- T *addHypervisorFuncEvent(const char *lbl)
- {
- return addFuncEvent<T>(hypervisorSymtab, lbl);
- }
-
- /** Add a function-based event to the openboot. */
- template <class T>
- T *addOpenbootFuncEvent(const char *lbl)
- {
- return addFuncEvent<T>(openbootSymtab, lbl);
- }
-
+ typedef ArmSystemParams Params;
+ ArmSystem(Params *p);
+ ~ArmSystem();
+
virtual Addr fixFuncEventAddr(Addr addr)
{
//XXX This may eventually have to do something useful.
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -287,7 +287,15 @@
return NoFault;
#else
- fatal("translate atomic not yet implemented\n");
+ SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
+ if (!sctlr.m) {
+ req->setPaddr(req->getVaddr());
+ return NoFault;
+ }
+ panic("MMU translation not implemented\n");
+ return NoFault;
+
+
#endif
}
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1,6 +1,37 @@
+/*
+ * Copyright (c) 2009 ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
-#include <arch/arm/utility.hh>
-#include <cpu/thread_context.hh>
+
+#include "arch/arm/faults.hh"
+#include "arch/arm/utility.hh"
+#include "cpu/thread_context.hh"
namespace ArmISA {
@@ -12,8 +43,18 @@
// FPEXC.EN = 0
- static Fault reset = new Reset();
+ static Fault reset = new Reset;
if (cpuId == 0)
reset->invoke(tc);
}
+uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
+#if FULL_SYSTEM
+ panic("getArgument() not implemented for ARM!\n");
+#else
+ panic("getArgument() only implemented for FULL_SYSTEM\n");
+ M5_DUMMY_RETURN
+#endif
+}
+
+}
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -125,6 +125,17 @@
{
panic("Copy Misc. Regs Not Implemented Yet\n");
}
+
+ void initCPU(ThreadContext *tc, int cpuId);
+
+ static inline bool
+ inUserMode(ThreadContext *tc)
+ {
+ return (tc->readMiscRegNoEffect(MISCREG_CPSR) & 0x1f) == MODE_USER;
+ }
+
+uint64_t getArgument(ThreadContext *tc, int number, bool fp);
+
};
diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript
new file mode 100644
--- /dev/null
+++ b/src/dev/arm/SConscript
@@ -0,0 +1,36 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2009 ARM Limited
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+
+Import('*')
+
+if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'arm':
+ SimObject('Versatile.py')
+
+ Source('versatile.cc')
diff --git a/src/dev/sparc/T1000.py b/src/dev/arm/Versatile.py
copy from src/dev/sparc/T1000.py
copy to src/dev/arm/Versatile.py
--- a/src/dev/sparc/T1000.py
+++ b/src/dev/arm/Versatile.py
@@ -1,4 +1,5 @@
# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 ARM Limited
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -34,101 +35,17 @@
from Uart import Uart8250
-class MmDisk(BasicPioDevice):
- type = 'MmDisk'
- image = Param.DiskImage("Disk Image")
- pio_addr = 0x1F40000000
-
-class DumbTOD(BasicPioDevice):
- type = 'DumbTOD'
- time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
- pio_addr = 0xfff0c1fff8
-
-class Iob(PioDevice):
- type = 'Iob'
- pio_latency = Param.Latency('1ns', "Programed IO latency in simticks")
-
-
-class T1000(Platform):
- type = 'T1000'
+class Versatile(Platform):
+ type = 'Versatile'
system = Param.System(Parent.any, "system")
- fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
- #warn_access="Accessing Clock Unit -- Unimplemented!")
-
- fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
- ret_data64=0x0000000000000000, update_data=False)
- #warn_access="Accessing Memory Banks -- Unimplemented!")
-
- fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
- #warn_access="Accessing JBI -- Unimplemented!")
-
- fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
- ret_data64=0x0000000000000001, update_data=True)
- #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
-
- fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
- ret_data64=0x0000000000000001, update_data=True)
- #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
-
- fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
- ret_data64=0x0000000000000001, update_data=True)
- #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
-
- fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
- ret_data64=0x0000000000000001, update_data=True)
- #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
-
- fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
- ret_data64=0x0000000000000000, update_data=True)
- #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
-
- fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
- ret_data64=0x0000000000000000, update_data=True)
- #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
-
- fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
- ret_data64=0x0000000000000000, update_data=True)
- #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
-
- fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
- ret_data64=0x0000000000000000, update_data=True)
- #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
-
- fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
- #warn_access="Accessing SSI -- Unimplemented!")
-
- hterm = Terminal()
- hvuart = Uart8250(pio_addr=0xfff0c2c000)
- htod = DumbTOD()
-
- pterm = Terminal()
- puart0 = Uart8250(pio_addr=0x1f10000000)
-
- iob = Iob()
# Attach I/O devices that are on chip
def attachOnChipIO(self, bus):
- self.iob.pio = bus.port
- self.htod.pio = bus.port
+ pass
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
- self.hvuart.terminal = self.hterm
- self.puart0.terminal = self.pterm
- self.fake_clk.pio = bus.port
- self.fake_membnks.pio = bus.port
- self.fake_l2_1.pio = bus.port
- self.fake_l2_2.pio = bus.port
- self.fake_l2_3.pio = bus.port
- self.fake_l2_4.pio = bus.port
- self.fake_l2esr_1.pio = bus.port
- self.fake_l2esr_2.pio = bus.port
- self.fake_l2esr_3.pio = bus.port
- self.fake_l2esr_4.pio = bus.port
- self.fake_ssi.pio = bus.port
- self.fake_jbi.pio = bus.port
- self.puart0.pio = bus.port
- self.hvuart.pio = bus.port
+ pass
diff --git a/src/dev/sparc/t1000.cc b/src/dev/arm/versatile.cc
copy from src/dev/sparc/t1000.cc
copy to src/dev/arm/versatile.cc
--- a/src/dev/sparc/t1000.cc
+++ b/src/dev/arm/versatile.cc
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2009 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,7 +30,7 @@
*/
/** @file
- * Implementation of T1000 platform.
+ * Implementation of Versatile platform.
*/
#include <deque>
@@ -38,15 +39,14 @@
#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
-#include "dev/sparc/t1000.hh"
+#include "dev/arm/versatile.hh"
#include "dev/terminal.hh"
#include "sim/system.hh"
using namespace std;
-//Should this be AlphaISA?
using namespace TheISA;
-T1000::T1000(const Params *p)
+Versatile::Versatile(const Params *p)
: Platform(p), system(p->system)
{
// set the back pointer from the system to myself
@@ -54,40 +54,40 @@
}
Tick
-T1000::intrFrequency()
+Versatile::intrFrequency()
{
panic("Need implementation\n");
M5_DUMMY_RETURN
}
void
-T1000::postConsoleInt()
+Versatile::postConsoleInt()
{
warn_once("Don't know what interrupt to post for console.\n");
//panic("Need implementation\n");
}
void
-T1000::clearConsoleInt()
+Versatile::clearConsoleInt()
{
warn_once("Don't know what interrupt to clear for console.\n");
//panic("Need implementation\n");
}
void
-T1000::postPciInt(int line)
+Versatile::postPciInt(int line)
{
panic("Need implementation\n");
}
void
-T1000::clearPciInt(int line)
+Versatile::clearPciInt(int line)
{
panic("Need implementation\n");
}
Addr
-T1000::pciToDma(Addr pciAddr) const
+Versatile::pciToDma(Addr pciAddr) const
{
panic("Need implementation\n");
M5_DUMMY_RETURN
@@ -95,28 +95,28 @@
Addr
-T1000::calcPciConfigAddr(int bus, int dev, int func)
+Versatile::calcPciConfigAddr(int bus, int dev, int func)
{
panic("Need implementation\n");
M5_DUMMY_RETURN
}
Addr
-T1000::calcPciIOAddr(Addr addr)
+Versatile::calcPciIOAddr(Addr addr)
{
panic("Need implementation\n");
M5_DUMMY_RETURN
}
Addr
-T1000::calcPciMemAddr(Addr addr)
+Versatile::calcPciMemAddr(Addr addr)
{
panic("Need implementation\n");
M5_DUMMY_RETURN
}
-T1000 *
-T1000Params::create()
+Versatile *
+VersatileParams::create()
{
- return new T1000(this);
+ return new Versatile(this);
}
diff --git a/src/dev/sparc/t1000.hh b/src/dev/arm/versatile.hh
copy from src/dev/sparc/t1000.hh
copy to src/dev/arm/versatile.hh
--- a/src/dev/sparc/t1000.hh
+++ b/src/dev/arm/versatile.hh
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2009 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,34 +31,34 @@
/**
* @file
- * Declaration of top level class for the T1000 platform chips. This class just
+ * Declaration of top level class for the Versatile platform chips. This class
just
* retains pointers to all its children so the children can communicate.
*/
-#ifndef __DEV_T1000_HH__
-#define __DEV_T1000_HH__
+#ifndef __DEV_ARM_VERSATILE_HH__
+#define __DEV_ARM_VERSATILE_HH__
#include "dev/platform.hh"
-#include "params/T1000.hh"
+#include "params/Versatile.hh"
class IdeController;
class System;
-class T1000 : public Platform
+class Versatile : public Platform
{
public:
/** Pointer to the system */
System *system;
public:
- typedef T1000Params Params;
+ typedef VersatileParams Params;
/**
* Constructor for the Tsunami Class.
* @param name name of the object
* @param s system the object belongs to
* @param intctrl pointer to the interrupt controller
*/
- T1000(const Params *p);
+ Versatile(const Params *p);
/**
* Return the interrupting frequency to AlphaAccess
@@ -104,4 +105,4 @@
virtual Addr calcPciMemAddr(Addr addr);
};
-#endif // __DEV_T1000_HH__
+#endif // __DEV_ARM_VERSATILE_HH__
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