# HG changeset patch
# User Ali Saidi <[email protected]>
# Date 1258399213 21600
# Node ID ffcbae38757b25a7643aa55f6abe61f53f7281bb
# Parent 4fbeb3ff43d35580a375defac4e4ae80181e541a
ARM: Fix style and associated problems with using namespace in header file.
diff --git a/src/arch/arm/insts/branch.cc b/src/arch/arm/insts/branch.cc
--- a/src/arch/arm/insts/branch.cc
+++ b/src/arch/arm/insts/branch.cc
@@ -30,7 +30,7 @@
#include "arch/arm/insts/branch.hh"
#include "base/loader/symtab.hh"
-namespace ArmISA
+namespace ArmISAInst
{
Addr
Branch::branchTarget(Addr branchPC) const
diff --git a/src/arch/arm/insts/branch.hh b/src/arch/arm/insts/branch.hh
--- a/src/arch/arm/insts/branch.hh
+++ b/src/arch/arm/insts/branch.hh
@@ -31,7 +31,7 @@
#include "arch/arm/insts/pred_inst.hh"
-namespace ArmISA
+namespace ArmISAInst
{
/**
* Base class for instructions whose disassembly is not purely a
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -31,7 +31,7 @@
#include "arch/arm/insts/pred_inst.hh"
-namespace ArmISA
+namespace ArmISAInst
{
static inline unsigned int
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -30,7 +30,7 @@
#include "arch/arm/insts/mem.hh"
#include "base/loader/symtab.hh"
-namespace ArmISA
+namespace ArmISAInst
{
std::string
Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -31,7 +31,7 @@
#include "arch/arm/insts/pred_inst.hh"
-namespace ArmISA
+namespace ArmISAInst
{
/**
* Base class for general Arm memory-format instructions.
diff --git a/src/arch/arm/insts/pred_inst.cc b/src/arch/arm/insts/pred_inst.cc
--- a/src/arch/arm/insts/pred_inst.cc
+++ b/src/arch/arm/insts/pred_inst.cc
@@ -29,7 +29,7 @@
#include "arch/arm/insts/pred_inst.hh"
-namespace ArmISA
+namespace ArmISAInst
{
std::string
PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -32,7 +32,7 @@
#include "arch/arm/insts/static_inst.hh"
#include "base/trace.hh"
-namespace ArmISA
+namespace ArmISAInst
{
static inline uint32_t
rotate_imm(uint32_t immValue, int rotateValue)
@@ -48,12 +48,12 @@
{
protected:
- ConditionCode condCode;
+ ArmISA::ConditionCode condCode;
/// Constructor
PredOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
ArmStaticInst(mnem, _machInst, __opClass),
- condCode((ConditionCode)(unsigned)machInst.condCode)
+ condCode((ArmISA::ConditionCode)(unsigned)machInst.condCode)
{
}
};
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -32,7 +32,9 @@
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
-namespace ArmISA
+using namespace ArmISA;
+
+namespace ArmISAInst
{
// Shift Rm by an immediate value
int32_t
diff --git a/src/arch/arm/insts/static_inst.hh
b/src/arch/arm/insts/static_inst.hh
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -32,7 +32,7 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
-namespace ArmISA
+namespace ArmISAInst
{
class ArmStaticInst : public StaticInst
{
@@ -76,10 +76,10 @@
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
static uint32_t
- cpsrWriteByInstr(CPSR cpsr, uint32_t val,
+ cpsrWriteByInstr(ArmISA::CPSR cpsr, uint32_t val,
uint8_t byteMask, bool affectState)
{
- bool privileged = (cpsr.mode != MODE_USER);
+ bool privileged = (cpsr.mode != ArmISA::MODE_USER);
uint32_t bitMask = 0;
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -40,173 +40,175 @@
namespace ArmISA
{
- class ISA
+
+class ISA
+{
+ protected:
+ MiscReg miscRegs[NumMiscRegs];
+ const IntRegIndex *intRegMap;
+
+ void
+ updateRegMap(CPSR cpsr)
{
- protected:
- MiscReg miscRegs[NumMiscRegs];
- const IntRegIndex *intRegMap;
+ switch (cpsr.mode) {
+ case MODE_USER:
+ case MODE_SYSTEM:
+ intRegMap = IntRegUsrMap;
+ break;
+ case MODE_FIQ:
+ intRegMap = IntRegFiqMap;
+ break;
+ case MODE_IRQ:
+ intRegMap = IntRegIrqMap;
+ break;
+ case MODE_SVC:
+ intRegMap = IntRegSvcMap;
+ break;
+ case MODE_MON:
+ intRegMap = IntRegMonMap;
+ break;
+ case MODE_ABORT:
+ intRegMap = IntRegAbtMap;
+ break;
+ case MODE_UNDEFINED:
+ intRegMap = IntRegUndMap;
+ break;
+ default:
+ panic("Unrecognized mode setting in CPSR.\n");
+ }
+ }
- void
- updateRegMap(CPSR cpsr)
- {
+ public:
+ void clear()
+ {
+ memset(miscRegs, 0, sizeof(miscRegs));
+ CPSR cpsr = 0;
+ cpsr.mode = MODE_USER;
+ miscRegs[MISCREG_CPSR] = cpsr;
+ updateRegMap(cpsr);
+
+ SCTLR sctlr = 0;
+ sctlr.nmfi = 1;
+ sctlr.rao1 = 1;
+ sctlr.rao2 = 1;
+ sctlr.rao3 = 1;
+ sctlr.rao4 = 1;
+
+ //XXX We need to initialize the rest of the state.
+ }
+
+ MiscReg
+ readMiscRegNoEffect(int misc_reg)
+ {
+ assert(misc_reg < NumMiscRegs);
+ if (misc_reg == MISCREG_SPSR) {
+ CPSR cpsr = miscRegs[MISCREG_CPSR];
switch (cpsr.mode) {
case MODE_USER:
- case MODE_SYSTEM:
- intRegMap = IntRegUsrMap;
- break;
+ return miscRegs[MISCREG_SPSR];
case MODE_FIQ:
- intRegMap = IntRegFiqMap;
- break;
+ return miscRegs[MISCREG_SPSR_FIQ];
case MODE_IRQ:
- intRegMap = IntRegIrqMap;
- break;
+ return miscRegs[MISCREG_SPSR_IRQ];
case MODE_SVC:
- intRegMap = IntRegSvcMap;
- break;
+ return miscRegs[MISCREG_SPSR_SVC];
case MODE_MON:
- intRegMap = IntRegMonMap;
- break;
+ return miscRegs[MISCREG_SPSR_MON];
case MODE_ABORT:
- intRegMap = IntRegAbtMap;
- break;
+ return miscRegs[MISCREG_SPSR_ABT];
case MODE_UNDEFINED:
- intRegMap = IntRegUndMap;
- break;
+ return miscRegs[MISCREG_SPSR_UND];
default:
- panic("Unrecognized mode setting in CPSR.\n");
+ return miscRegs[MISCREG_SPSR];
}
}
+ return miscRegs[misc_reg];
+ }
- public:
- void clear()
- {
- memset(miscRegs, 0, sizeof(miscRegs));
- CPSR cpsr = 0;
- cpsr.mode = MODE_USER;
- miscRegs[MISCREG_CPSR] = cpsr;
- updateRegMap(cpsr);
+ MiscReg
+ readMiscReg(int misc_reg, ThreadContext *tc)
+ {
+ return readMiscRegNoEffect(misc_reg);
+ }
- SCTLR sctlr = 0;
- sctlr.nmfi = 1;
- sctlr.rao1 = 1;
- sctlr.rao2 = 1;
- sctlr.rao3 = 1;
- sctlr.rao4 = 1;
-
- //XXX We need to initialize the rest of the state.
- }
-
- MiscReg
- readMiscRegNoEffect(int misc_reg)
- {
- assert(misc_reg < NumMiscRegs);
- if (misc_reg == MISCREG_SPSR) {
- CPSR cpsr = miscRegs[MISCREG_CPSR];
- switch (cpsr.mode) {
- case MODE_USER:
- return miscRegs[MISCREG_SPSR];
- case MODE_FIQ:
- return miscRegs[MISCREG_SPSR_FIQ];
- case MODE_IRQ:
- return miscRegs[MISCREG_SPSR_IRQ];
- case MODE_SVC:
- return miscRegs[MISCREG_SPSR_SVC];
- case MODE_MON:
- return miscRegs[MISCREG_SPSR_MON];
- case MODE_ABORT:
- return miscRegs[MISCREG_SPSR_ABT];
- case MODE_UNDEFINED:
- return miscRegs[MISCREG_SPSR_UND];
- default:
- return miscRegs[MISCREG_SPSR];
- }
- }
- return miscRegs[misc_reg];
- }
-
- MiscReg
- readMiscReg(int misc_reg, ThreadContext *tc)
- {
- return readMiscRegNoEffect(misc_reg);
- }
-
- void
- setMiscRegNoEffect(int misc_reg, const MiscReg &val)
- {
- assert(misc_reg < NumMiscRegs);
- if (misc_reg == MISCREG_SPSR) {
- CPSR cpsr = miscRegs[MISCREG_CPSR];
- switch (cpsr.mode) {
- case MODE_USER:
- miscRegs[MISCREG_SPSR] = val;
- return;
- case MODE_FIQ:
- miscRegs[MISCREG_SPSR_FIQ] = val;
- return;
- case MODE_IRQ:
- miscRegs[MISCREG_SPSR_IRQ] = val;
- return;
- case MODE_SVC:
- miscRegs[MISCREG_SPSR_SVC] = val;
- return;
- case MODE_MON:
- miscRegs[MISCREG_SPSR_MON] = val;
- return;
- case MODE_ABORT:
- miscRegs[MISCREG_SPSR_ABT] = val;
- return;
- case MODE_UNDEFINED:
- miscRegs[MISCREG_SPSR_UND] = val;
- return;
- default:
- miscRegs[MISCREG_SPSR] = val;
- return;
- }
- }
- miscRegs[misc_reg] = val;
- }
-
- void
- setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
- {
- if (misc_reg == MISCREG_CPSR) {
- updateRegMap(val);
- }
- return setMiscRegNoEffect(misc_reg, val);
- }
-
- int
- flattenIntIndex(int reg)
- {
- assert(reg >= 0);
- if (reg < NUM_ARCH_INTREGS) {
- return intRegMap[reg];
- } else if (reg < NUM_INTREGS) {
- return reg;
- } else {
- reg -= NUM_INTREGS;
- assert(reg < NUM_ARCH_INTREGS);
- return reg;
+ void
+ setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ {
+ assert(misc_reg < NumMiscRegs);
+ if (misc_reg == MISCREG_SPSR) {
+ CPSR cpsr = miscRegs[MISCREG_CPSR];
+ switch (cpsr.mode) {
+ case MODE_USER:
+ miscRegs[MISCREG_SPSR] = val;
+ return;
+ case MODE_FIQ:
+ miscRegs[MISCREG_SPSR_FIQ] = val;
+ return;
+ case MODE_IRQ:
+ miscRegs[MISCREG_SPSR_IRQ] = val;
+ return;
+ case MODE_SVC:
+ miscRegs[MISCREG_SPSR_SVC] = val;
+ return;
+ case MODE_MON:
+ miscRegs[MISCREG_SPSR_MON] = val;
+ return;
+ case MODE_ABORT:
+ miscRegs[MISCREG_SPSR_ABT] = val;
+ return;
+ case MODE_UNDEFINED:
+ miscRegs[MISCREG_SPSR_UND] = val;
+ return;
+ default:
+ miscRegs[MISCREG_SPSR] = val;
+ return;
}
}
+ miscRegs[misc_reg] = val;
+ }
- int
- flattenFloatIndex(int reg)
- {
+ void
+ setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
+ {
+ if (misc_reg == MISCREG_CPSR) {
+ updateRegMap(val);
+ }
+ return setMiscRegNoEffect(misc_reg, val);
+ }
+
+ int
+ flattenIntIndex(int reg)
+ {
+ assert(reg >= 0);
+ if (reg < NUM_ARCH_INTREGS) {
+ return intRegMap[reg];
+ } else if (reg < NUM_INTREGS) {
+ return reg;
+ } else {
+ reg -= NUM_INTREGS;
+ assert(reg < NUM_ARCH_INTREGS);
return reg;
}
+ }
- void serialize(EventManager *em, std::ostream &os)
- {}
- void unserialize(EventManager *em, Checkpoint *cp,
- const std::string §ion)
- {}
+ int
+ flattenFloatIndex(int reg)
+ {
+ return reg;
+ }
- ISA()
- {
- clear();
- }
- };
-}
+ void serialize(EventManager *em, std::ostream &os)
+ {}
+ void unserialize(EventManager *em, Checkpoint *cp,
+ const std::string §ion)
+ {}
+
+ ISA()
+ {
+ clear();
+ }
+};
+
+} // namespace ArmISA
#endif
diff --git a/src/arch/arm/isa/formats/util.isa
b/src/arch/arm/isa/formats/util.isa
--- a/src/arch/arm/isa/formats/util.isa
+++ b/src/arch/arm/isa/formats/util.isa
@@ -78,7 +78,7 @@
output header {{
- std::string inst2string(MachInst machInst);
+ std::string inst2string(ArmISA::MachInst machInst);
StaticInstPtr gen_ldrstr_uop(uint32_t baseinst, int loadop, uint32_t
rd, int32_t disp);
int emit_ldfstf_uops(StaticInstPtr* microOps, int index, uint32_t
baseinst, int loadop, int up, int32_t disp);
}};
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -44,70 +44,69 @@
namespace ArmISA
{
- using namespace LittleEndianGuest;
- StaticInstPtr decodeInst(ExtMachInst);
+using namespace LittleEndianGuest;
- // ARM DOES NOT have a delay slot
- #define ISA_HAS_DELAY_SLOT 0
+StaticInstPtr decodeInst(ExtMachInst);
- const Addr PageShift = 12;
- const Addr PageBytes = ULL(1) << PageShift;
- const Addr Page_Mask = ~(PageBytes - 1);
- const Addr PageOffset = PageBytes - 1;
+// ARM DOES NOT have a delay slot
+#define ISA_HAS_DELAY_SLOT 0
+const Addr PageShift = 12;
+const Addr PageBytes = ULL(1) << PageShift;
+const Addr Page_Mask = ~(PageBytes - 1);
+const Addr PageOffset = PageBytes - 1;
- ////////////////////////////////////////////////////////////////////////
- //
- // Translation stuff
- //
- const Addr PteShift = 3;
- const Addr NPtePageShift = PageShift - PteShift;
- const Addr NPtePage = ULL(1) << NPtePageShift;
- const Addr PteMask = NPtePage - 1;
+////////////////////////////////////////////////////////////////////////
+//
+// Translation stuff
+//
- //// All 'Mapped' segments go through the TLB
- //// All other segments are translated by dropping the MSB, to give
- //// the corresponding physical address
- // User Segment - Mapped
- const Addr USegBase = ULL(0x0);
- const Addr USegEnd = ULL(0x7FFFFFFF);
+const Addr PteShift = 3;
+const Addr NPtePageShift = PageShift - PteShift;
+const Addr NPtePage = ULL(1) << NPtePageShift;
+const Addr PteMask = NPtePage - 1;
- // Kernel Segment 0 - Unmapped
- const Addr KSeg0End = ULL(0x9FFFFFFF);
- const Addr KSeg0Base = ULL(0x80000000);
- const Addr KSeg0Mask = ULL(0x1FFFFFFF);
+//// All 'Mapped' segments go through the TLB
+//// All other segments are translated by dropping the MSB, to give
+//// the corresponding physical address
+// User Segment - Mapped
+const Addr USegBase = ULL(0x0);
+const Addr USegEnd = ULL(0x7FFFFFFF);
- // For loading... XXX This maybe could be USegEnd?? --ali
- const Addr LoadAddrMask = ULL(0xffffffffff);
+// Kernel Segment 0 - Unmapped
+const Addr KSeg0End = ULL(0x9FFFFFFF);
+const Addr KSeg0Base = ULL(0x80000000);
+const Addr KSeg0Mask = ULL(0x1FFFFFFF);
- const unsigned VABits = 32;
- const unsigned PABits = 32; // Is this correct?
- const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
- const Addr VAddrUnImplMask = ~VAddrImplMask;
- inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
- inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; }
- inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; }
+// For loading... XXX This maybe could be USegEnd?? --ali
+const Addr LoadAddrMask = ULL(0xffffffffff);
- const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
+const unsigned VABits = 32;
+const unsigned PABits = 32; // Is this correct?
+const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
+const Addr VAddrUnImplMask = ~VAddrImplMask;
+inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
+inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; }
+inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; }
- // return a no-op instruction... used for instruction fetch faults
- const ExtMachInst NoopMachInst = 0x00000000;
+const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
- const int LogVMPageSize = 12; // 4K bytes
- const int VMPageSize = (1 << LogVMPageSize);
+// return a no-op instruction... used for instruction fetch faults
+const ExtMachInst NoopMachInst = 0x00000000;
- const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
+const int LogVMPageSize = 12; // 4K bytes
+const int VMPageSize = (1 << LogVMPageSize);
- const int MachineBytes = 4;
- const int WordBytes = 4;
- const int HalfwordBytes = 2;
- const int ByteBytes = 1;
+const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
- const uint32_t HighVecs = 0xFFFF0000;
-};
+const int MachineBytes = 4;
+const int WordBytes = 4;
+const int HalfwordBytes = 2;
+const int ByteBytes = 1;
-using namespace ArmISA;
+const uint32_t HighVecs = 0xFFFF0000;
+}; // namespace ArmISA
#endif // __ARCH_ARM_ISA_TRAITS_HH__
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -34,93 +34,96 @@
namespace ArmISA
{
- enum ConditionCode {
- COND_EQ = 0,
- COND_NE, // 1
- COND_CS, // 2
- COND_CC, // 3
- COND_MI, // 4
- COND_PL, // 5
- COND_VS, // 6
- COND_VC, // 7
- COND_HI, // 8
- COND_LS, // 9
- COND_GE, // 10
- COND_LT, // 11
- COND_GT, // 12
- COND_LE, // 13
- COND_AL, // 14
- COND_NV // 15
- };
- enum MiscRegIndex {
- MISCREG_CPSR = 0,
- MISCREG_SPSR,
- MISCREG_SPSR_FIQ,
- MISCREG_SPSR_IRQ,
- MISCREG_SPSR_SVC,
- MISCREG_SPSR_MON,
- MISCREG_SPSR_UND,
- MISCREG_SPSR_ABT,
- MISCREG_FPSR,
- MISCREG_FPSID,
- MISCREG_FPSCR,
- MISCREG_FPEXC,
- MISCREG_SCTLR,
- NUM_MISCREGS
- };
-
- const char * const miscRegName[NUM_MISCREGS] = {
- "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und",
- "spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "sctlr"
- };
-
- BitUnion32(CPSR)
- Bitfield<31> n;
- Bitfield<30> z;
- Bitfield<29> c;
- Bitfield<28> v;
- Bitfield<27> q;
- Bitfield<26,25> it1;
- Bitfield<24> j;
- Bitfield<19, 16> ge;
- Bitfield<15,10> it2;
- Bitfield<9> e;
- Bitfield<8> a;
- Bitfield<7> i;
- Bitfield<6> f;
- Bitfield<5> t;
- Bitfield<4, 0> mode;
- EndBitUnion(CPSR)
-
- // This mask selects bits of the CPSR that actually go in the CondCodes
- // integer register to allow renaming.
- static const uint32_t CondCodesMask = 0xF80F0000;
-
- BitUnion32(SCTLR)
- Bitfield<30> te; // Thumb Exception Enable
- Bitfield<29> afe; // Access flag enable
- Bitfield<28> tre; // TEX Remap bit
- Bitfield<27> nmfi;// Non-maskable fast interrupts enable
- Bitfield<25> ee; // Exception Endianness bit
- Bitfield<24> ve; // Interrupt vectors enable
- Bitfield<23> rao1;// Read as one
- Bitfield<22> u; // Alignment (now unused)
- Bitfield<21> fi; // Fast interrupts configuration enable
- Bitfield<18> rao2;// Read as one
- Bitfield<17> ha; // Hardware access flag enable
- Bitfield<16> rao3;// Read as one
- Bitfield<14> rr; // Round robin cache replacement
- Bitfield<13> v; // Base address for exception vectors
- Bitfield<12> i; // instruction cache enable
- Bitfield<11> z; // branch prediction enable bit
- Bitfield<10> sw; // Enable swp/swpb
- Bitfield<6,3> rao4;// Read as one
- Bitfield<7> b; // Endianness support (unused)
- Bitfield<2> c; // Cache enable bit
- Bitfield<1> a; // Alignment fault checking
- Bitfield<0> m; // MMU enable bit
- EndBitUnion(SCTLR)
+enum ConditionCode {
+ COND_EQ = 0,
+ COND_NE, // 1
+ COND_CS, // 2
+ COND_CC, // 3
+ COND_MI, // 4
+ COND_PL, // 5
+ COND_VS, // 6
+ COND_VC, // 7
+ COND_HI, // 8
+ COND_LS, // 9
+ COND_GE, // 10
+ COND_LT, // 11
+ COND_GT, // 12
+ COND_LE, // 13
+ COND_AL, // 14
+ COND_NV // 15
};
+enum MiscRegIndex {
+ MISCREG_CPSR = 0,
+ MISCREG_SPSR,
+ MISCREG_SPSR_FIQ,
+ MISCREG_SPSR_IRQ,
+ MISCREG_SPSR_SVC,
+ MISCREG_SPSR_MON,
+ MISCREG_SPSR_UND,
+ MISCREG_SPSR_ABT,
+ MISCREG_FPSR,
+ MISCREG_FPSID,
+ MISCREG_FPSCR,
+ MISCREG_FPEXC,
+ MISCREG_SCTLR,
+ NUM_MISCREGS
+};
+
+const char * const miscRegName[NUM_MISCREGS] = {
+ "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und",
+ "spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "sctlr"
+};
+
+BitUnion32(CPSR)
+ Bitfield<31> n;
+ Bitfield<30> z;
+ Bitfield<29> c;
+ Bitfield<28> v;
+ Bitfield<27> q;
+ Bitfield<26,25> it1;
+ Bitfield<24> j;
+ Bitfield<19, 16> ge;
+ Bitfield<15,10> it2;
+ Bitfield<9> e;
+ Bitfield<8> a;
+ Bitfield<7> i;
+ Bitfield<6> f;
+ Bitfield<5> t;
+ Bitfield<4, 0> mode;
+EndBitUnion(CPSR)
+
+// This mask selects bits of the CPSR that actually go in the CondCodes
+// integer register to allow renaming.
+static const uint32_t CondCodesMask = 0xF80F0000;
+
+BitUnion32(SCTLR)
+ Bitfield<30> te; // Thumb Exception Enable
+ Bitfield<29> afe; // Access flag enable
+ Bitfield<28> tre; // TEX Remap bit
+ Bitfield<27> nmfi;// Non-maskable fast interrupts enable
+ Bitfield<25> ee; // Exception Endianness bit
+ Bitfield<24> ve; // Interrupt vectors enable
+ Bitfield<23> rao1;// Read as one
+ Bitfield<22> u; // Alignment (now unused)
+ Bitfield<21> fi; // Fast interrupts configuration enable
+ Bitfield<18> rao2;// Read as one
+ Bitfield<17> ha; // Hardware access flag enable
+ Bitfield<16> rao3;// Read as one
+ Bitfield<14> rr; // Round robin cache replacement
+ Bitfield<13> v; // Base address for exception vectors
+ Bitfield<12> i; // instruction cache enable
+ Bitfield<11> z; // branch prediction enable bit
+ Bitfield<10> sw; // Enable swp/swpb
+ Bitfield<6,3> rao4;// Read as one
+ Bitfield<7> b; // Endianness support (unused)
+ Bitfield<2> c; // Cache enable bit
+ Bitfield<1> a; // Alignment fault checking
+ Bitfield<0> m; // MMU enable bit
+EndBitUnion(SCTLR)
+
+
+}; //namespace ArmISA
+
#endif // __ARCH_ARM_MISCREGS_HH__
diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -34,6 +34,8 @@
#include "cpu/thread_context.hh"
#include "params/ArmNativeTrace.hh"
+using namespace ArmISA;
+
namespace Trace {
#if TRACING_ON
diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -43,60 +43,60 @@
namespace ArmISA {
- struct VAddr
- {
- static const int ImplBits = 43;
- static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
- static const Addr UnImplMask = ~ImplMask;
+struct VAddr
+{
+ static const int ImplBits = 43;
+ static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
+ static const Addr UnImplMask = ~ImplMask;
- VAddr(Addr a) : addr(a) {}
- Addr addr;
- operator Addr() const { return addr; }
- const VAddr &operator=(Addr a) { addr = a; return *this; }
+ VAddr(Addr a) : addr(a) {}
+ Addr addr;
+ operator Addr() const { return addr; }
+ const VAddr &operator=(Addr a) { addr = a; return *this; }
- Addr vpn() const { return (addr & ImplMask) >> PageShift; }
- Addr page() const { return addr & Page_Mask; }
- Addr offset() const { return addr & PageOffset; }
+ Addr vpn() const { return (addr & ImplMask) >> PageShift; }
+ Addr page() const { return addr & Page_Mask; }
+ Addr offset() const { return addr & PageOffset; }
- Addr level3() const
- { return ArmISA::PteAddr(addr >> PageShift); }
- Addr level2() const
- { return ArmISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
- Addr level1() const
- { return ArmISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
- };
+ Addr level3() const
+ { return ArmISA::PteAddr(addr >> PageShift); }
+ Addr level2() const
+ { return ArmISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
+ Addr level1() const
+ { return ArmISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
+};
- // ITB/DTB page table entry
- struct PTE
- {
- Addr Mask; // What parts of the VAddr (from bits 28..11) should be used
in translation (includes Mask and MaskX from PageMask)
- Addr VPN; // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits
31..11 from EntryHi)
- uint8_t asid; // Address Space ID (8 bits) // Lower 8 bits of EntryHi
+// ITB/DTB page table entry
+struct PTE
+{
+ Addr Mask; // What parts of the VAddr (from bits 28..11) should be used in
translation (includes Mask and MaskX from PageMask)
+ Addr VPN; // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11
from EntryHi)
+ uint8_t asid; // Address Space ID (8 bits) // Lower 8 bits of EntryHi
- bool G; // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1
G bit
+ bool G; // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G
bit
- /* Contents of Entry Lo0 */
- Addr PFN0; // Physical Frame Number - Even
- bool D0; // Even entry Dirty Bit
- bool V0; // Even entry Valid Bit
- uint8_t C0; // Cache Coherency Bits - Even
+ /* Contents of Entry Lo0 */
+ Addr PFN0; // Physical Frame Number - Even
+ bool D0; // Even entry Dirty Bit
+ bool V0; // Even entry Valid Bit
+ uint8_t C0; // Cache Coherency Bits - Even
- /* Contents of Entry Lo1 */
- Addr PFN1; // Physical Frame Number - Odd
- bool D1; // Odd entry Dirty Bit
- bool V1; // Odd entry Valid Bit
- uint8_t C1; // Cache Coherency Bits (3 bits)
+ /* Contents of Entry Lo1 */
+ Addr PFN1; // Physical Frame Number - Odd
+ bool D1; // Odd entry Dirty Bit
+ bool V1; // Odd entry Valid Bit
+ uint8_t C1; // Cache Coherency Bits (3 bits)
- /* The next few variables are put in as optimizations to reduce TLB
lookup overheads */
- /* For a given Mask, what is the address shift amount, and what is the
OffsetMask */
- int AddrShiftAmount;
- int OffsetMask;
+ /* The next few variables are put in as optimizations to reduce TLB lookup
overheads */
+ /* For a given Mask, what is the address shift amount, and what is the
OffsetMask */
+ int AddrShiftAmount;
+ int OffsetMask;
- bool Valid() { return (V0 | V1);};
- void serialize(std::ostream &os);
- void unserialize(Checkpoint *cp, const std::string §ion);
- };
+ bool Valid() { return (V0 | V1);};
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
+};
-};
+}; //namespace ArmISA
#endif // __ARCH_ARM_PAGETABLE_H__
diff --git a/src/arch/arm/predecoder.hh b/src/arch/arm/predecoder.hh
--- a/src/arch/arm/predecoder.hh
+++ b/src/arch/arm/predecoder.hh
@@ -41,65 +41,68 @@
namespace ArmISA
{
- class Predecoder
+
+class Predecoder
+{
+ protected:
+ ThreadContext * tc;
+ //The extended machine instruction being generated
+ ExtMachInst emi;
+
+ public:
+ Predecoder(ThreadContext * _tc) : tc(_tc)
+ {}
+
+ ThreadContext * getTC()
{
- protected:
- ThreadContext * tc;
- //The extended machine instruction being generated
- ExtMachInst emi;
+ return tc;
+ }
- public:
- Predecoder(ThreadContext * _tc) : tc(_tc)
- {}
+ void setTC(ThreadContext * _tc)
+ {
+ tc = _tc;
+ }
- ThreadContext * getTC()
- {
- return tc;
- }
+ void process()
+ {}
- void setTC(ThreadContext * _tc)
- {
- tc = _tc;
- }
+ void reset()
+ {}
- void process()
- {}
+ //Use this to give data to the predecoder. This should be used
+ //when there is control flow.
+ void moreBytes(Addr pc, Addr fetchPC, MachInst inst)
+ {
+ emi = inst;
+ emi.sevenAndFour = bits(inst, 7) && bits(inst, 4);
+ emi.isMisc = (bits(inst, 24, 23) == 0x2 && bits(inst, 20) == 0);
+ }
- void reset()
- {}
+ //Use this to give data to the predecoder. This should be used
+ //when instructions are executed in order.
+ void moreBytes(MachInst machInst)
+ {
+ moreBytes(0, 0, machInst);
+ }
- //Use this to give data to the predecoder. This should be used
- //when there is control flow.
- void moreBytes(Addr pc, Addr fetchPC, MachInst inst)
- {
- emi = inst;
- emi.sevenAndFour = bits(inst, 7) && bits(inst, 4);
- emi.isMisc = (bits(inst, 24, 23) == 0x2 && bits(inst, 20) == 0);
- }
+ bool needMoreBytes()
+ {
+ return true;
+ }
- //Use this to give data to the predecoder. This should be used
- //when instructions are executed in order.
- void moreBytes(MachInst machInst)
- {
- moreBytes(0, 0, machInst);
- }
+ bool extMachInstReady()
+ {
+ return true;
+ }
- bool needMoreBytes()
- {
- return true;
- }
-
- bool extMachInstReady()
- {
- return true;
- }
-
- //This returns a constant reference to the ExtMachInst to avoid a copy
- const ExtMachInst & getExtMachInst()
- {
- return emi;
- }
- };
+ //This returns a constant reference to the ExtMachInst to avoid a copy
+ const ExtMachInst & getExtMachInst()
+ {
+ return emi;
+ }
};
+
+}; // namespace ArmISA
+
#endif // __ARCH_ARM_PREDECODER_HH__
diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -37,30 +37,33 @@
namespace ArmISA
{
- class RemoteGDB : public BaseRemoteGDB
- {
- public:
- //These needs to be written to suit ARM
- RemoteGDB(System *system, ThreadContext *context)
- : BaseRemoteGDB(system, context, 1)
- {}
+class RemoteGDB : public BaseRemoteGDB
+{
+ public:
+ //These needs to be written to suit ARM
- bool acc(Addr, size_t)
- { panic("acc not implemented for ARM!"); }
+ RemoteGDB(System *system, ThreadContext *context)
+ : BaseRemoteGDB(system, context, 1)
+ {}
- void getregs()
- { panic("getregs not implemented for ARM!"); }
+ bool acc(Addr, size_t)
+ { panic("acc not implemented for ARM!"); }
- void setregs()
- { panic("setregs not implemented for ARM!"); }
+ void getregs()
+ { panic("getregs not implemented for ARM!"); }
- void clearSingleStep()
- { panic("clearSingleStep not implemented for ARM!"); }
+ void setregs()
+ { panic("setregs not implemented for ARM!"); }
- void setSingleStep()
- { panic("setSingleStep not implemented for ARM!"); }
- };
-}
+ void clearSingleStep()
+ { panic("clearSingleStep not implemented for ARM!"); }
+
+ void setSingleStep()
+ { panic("setSingleStep not implemented for ARM!"); }
+};
+
+
+} //namespace ArmISA
#endif /* __ARCH_ARM_REMOTE_GDB_H__ */
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -36,138 +36,139 @@
namespace ArmISA
{
- typedef uint32_t MachInst;
- BitUnion64(ExtMachInst)
- // Made up bitfields that make life easier.
- Bitfield<33> sevenAndFour;
- Bitfield<32> isMisc;
+typedef uint32_t MachInst;
- // All the different types of opcode fields.
- Bitfield<27, 25> encoding;
- Bitfield<25> useImm;
- Bitfield<24, 21> opcode;
- Bitfield<24, 20> mediaOpcode;
- Bitfield<24> opcode24;
- Bitfield<23, 20> opcode23_20;
- Bitfield<23, 21> opcode23_21;
- Bitfield<20> opcode20;
- Bitfield<22> opcode22;
- Bitfield<19> opcode19;
- Bitfield<18> opcode18;
- Bitfield<15, 12> opcode15_12;
- Bitfield<15> opcode15;
- Bitfield<7, 4> miscOpcode;
- Bitfield<7> opcode7;
- Bitfield<4> opcode4;
+BitUnion64(ExtMachInst)
+ // Made up bitfields that make life easier.
+ Bitfield<33> sevenAndFour;
+ Bitfield<32> isMisc;
- Bitfield<31, 28> condCode;
- Bitfield<20> sField;
- Bitfield<19, 16> rn;
- Bitfield<15, 12> rd;
- Bitfield<11, 7> shiftSize;
- Bitfield<6, 5> shift;
- Bitfield<3, 0> rm;
+ // All the different types of opcode fields.
+ Bitfield<27, 25> encoding;
+ Bitfield<25> useImm;
+ Bitfield<24, 21> opcode;
+ Bitfield<24, 20> mediaOpcode;
+ Bitfield<24> opcode24;
+ Bitfield<23, 20> opcode23_20;
+ Bitfield<23, 21> opcode23_21;
+ Bitfield<20> opcode20;
+ Bitfield<22> opcode22;
+ Bitfield<19> opcode19;
+ Bitfield<18> opcode18;
+ Bitfield<15, 12> opcode15_12;
+ Bitfield<15> opcode15;
+ Bitfield<7, 4> miscOpcode;
+ Bitfield<7> opcode7;
+ Bitfield<4> opcode4;
- Bitfield<11, 8> rs;
+ Bitfield<31, 28> condCode;
+ Bitfield<20> sField;
+ Bitfield<19, 16> rn;
+ Bitfield<15, 12> rd;
+ Bitfield<11, 7> shiftSize;
+ Bitfield<6, 5> shift;
+ Bitfield<3, 0> rm;
- SubBitUnion(puswl, 24, 20)
- Bitfield<24> prepost;
- Bitfield<23> up;
- Bitfield<22> psruser;
- Bitfield<21> writeback;
- Bitfield<20> loadOp;
- EndSubBitUnion(puswl)
+ Bitfield<11, 8> rs;
- Bitfield<24, 20> pubwl;
+ SubBitUnion(puswl, 24, 20)
+ Bitfield<24> prepost;
+ Bitfield<23> up;
+ Bitfield<22> psruser;
+ Bitfield<21> writeback;
+ Bitfield<20> loadOp;
+ EndSubBitUnion(puswl)
- Bitfield<7, 0> imm;
+ Bitfield<24, 20> pubwl;
- Bitfield<11, 8> rotate;
+ Bitfield<7, 0> imm;
- Bitfield<11, 0> immed11_0;
- Bitfield<7, 0> immed7_0;
+ Bitfield<11, 8> rotate;
- Bitfield<11, 8> immedHi11_8;
- Bitfield<3, 0> immedLo3_0;
+ Bitfield<11, 0> immed11_0;
+ Bitfield<7, 0> immed7_0;
- Bitfield<15, 0> regList;
-
- Bitfield<23, 0> offset;
-
- Bitfield<23, 0> immed23_0;
+ Bitfield<11, 8> immedHi11_8;
+ Bitfield<3, 0> immedLo3_0;
- Bitfield<11, 8> cpNum;
- Bitfield<18, 16> fn;
- Bitfield<14, 12> fd;
- Bitfield<3> fpRegImm;
- Bitfield<3, 0> fm;
- Bitfield<2, 0> fpImm;
- Bitfield<24, 20> punwl;
+ Bitfield<15, 0> regList;
+
+ Bitfield<23, 0> offset;
+
+ Bitfield<23, 0> immed23_0;
- Bitfield<7, 0> m5Func;
- EndBitUnion(ExtMachInst)
+ Bitfield<11, 8> cpNum;
+ Bitfield<18, 16> fn;
+ Bitfield<14, 12> fd;
+ Bitfield<3> fpRegImm;
+ Bitfield<3, 0> fm;
+ Bitfield<2, 0> fpImm;
+ Bitfield<24, 20> punwl;
- // Shift types for ARM instructions
- enum ArmShiftType {
- LSL = 0,
- LSR,
- ASR,
- ROR
- };
+ Bitfield<7, 0> m5Func;
+EndBitUnion(ExtMachInst)
- typedef uint64_t LargestRead;
- // Need to use 64 bits to make sure that read requests get handled properly
+// Shift types for ARM instructions
+enum ArmShiftType {
+ LSL = 0,
+ LSR,
+ ASR,
+ ROR
+};
- typedef int RegContextParam;
- typedef int RegContextVal;
+typedef uint64_t LargestRead;
+// Need to use 64 bits to make sure that read requests get handled properly
- //used in FP convert & round function
- enum ConvertType{
- SINGLE_TO_DOUBLE,
- SINGLE_TO_WORD,
- SINGLE_TO_LONG,
+typedef int RegContextParam;
+typedef int RegContextVal;
- DOUBLE_TO_SINGLE,
- DOUBLE_TO_WORD,
- DOUBLE_TO_LONG,
+//used in FP convert & round function
+enum ConvertType{
+ SINGLE_TO_DOUBLE,
+ SINGLE_TO_WORD,
+ SINGLE_TO_LONG,
- LONG_TO_SINGLE,
- LONG_TO_DOUBLE,
- LONG_TO_WORD,
- LONG_TO_PS,
+ DOUBLE_TO_SINGLE,
+ DOUBLE_TO_WORD,
+ DOUBLE_TO_LONG,
- WORD_TO_SINGLE,
- WORD_TO_DOUBLE,
- WORD_TO_LONG,
- WORD_TO_PS,
+ LONG_TO_SINGLE,
+ LONG_TO_DOUBLE,
+ LONG_TO_WORD,
+ LONG_TO_PS,
- PL_TO_SINGLE,
- PU_TO_SINGLE
- };
+ WORD_TO_SINGLE,
+ WORD_TO_DOUBLE,
+ WORD_TO_LONG,
+ WORD_TO_PS,
- //used in FP convert & round function
- enum RoundMode{
- RND_ZERO,
- RND_DOWN,
- RND_UP,
- RND_NEAREST
- };
+ PL_TO_SINGLE,
+ PU_TO_SINGLE
+};
- enum OperatingMode {
- MODE_USER = 16,
- MODE_FIQ = 17,
- MODE_IRQ = 18,
- MODE_SVC = 19,
- MODE_MON = 22,
- MODE_ABORT = 23,
- MODE_UNDEFINED = 27,
- MODE_SYSTEM = 31
- };
+//used in FP convert & round function
+enum RoundMode{
+ RND_ZERO,
+ RND_DOWN,
+ RND_UP,
+ RND_NEAREST
+};
- struct CoreSpecific {
- // Empty for now on the ARM
- };
+enum OperatingMode {
+ MODE_USER = 16,
+ MODE_FIQ = 17,
+ MODE_IRQ = 18,
+ MODE_SVC = 19,
+ MODE_MON = 22,
+ MODE_ABORT = 23,
+ MODE_UNDEFINED = 27,
+ MODE_SYSTEM = 31
+};
+
+struct CoreSpecific {
+ // Empty for now on the ARM
+};
} // namespace ArmISA
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -50,89 +50,89 @@
namespace ArmISA {
- inline bool
- testPredicate(CPSR cpsr, ConditionCode code)
+inline bool
+testPredicate(CPSR cpsr, ConditionCode code)
+{
+ switch (code)
{
- switch (code)
- {
- case COND_EQ: return cpsr.z;
- case COND_NE: return !cpsr.z;
- case COND_CS: return cpsr.c;
- case COND_CC: return !cpsr.c;
- case COND_MI: return cpsr.n;
- case COND_PL: return !cpsr.n;
- case COND_VS: return cpsr.v;
- case COND_VC: return !cpsr.v;
- case COND_HI: return (cpsr.c && !cpsr.z);
- case COND_LS: return !(cpsr.c && !cpsr.z);
- case COND_GE: return !(cpsr.n ^ cpsr.v);
- case COND_LT: return (cpsr.n ^ cpsr.v);
- case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z);
- case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z);
- case COND_AL: return true;
- case COND_NV: return false;
- default:
- panic("Unhandled predicate condition: %d\n", code);
- }
+ case COND_EQ: return cpsr.z;
+ case COND_NE: return !cpsr.z;
+ case COND_CS: return cpsr.c;
+ case COND_CC: return !cpsr.c;
+ case COND_MI: return cpsr.n;
+ case COND_PL: return !cpsr.n;
+ case COND_VS: return cpsr.v;
+ case COND_VC: return !cpsr.v;
+ case COND_HI: return (cpsr.c && !cpsr.z);
+ case COND_LS: return !(cpsr.c && !cpsr.z);
+ case COND_GE: return !(cpsr.n ^ cpsr.v);
+ case COND_LT: return (cpsr.n ^ cpsr.v);
+ case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z);
+ case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z);
+ case COND_AL: return true;
+ case COND_NV: return false;
+ default:
+ panic("Unhandled predicate condition: %d\n", code);
}
+}
- /**
- * Function to insure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
- template <class TC>
- void zeroRegisters(TC *tc);
+/**
+ * Function to insure ISA semantics about 0 registers.
+ * @param tc The thread context.
+ */
+template <class TC>
+void zeroRegisters(TC *tc);
- // Instruction address compression hooks
- static inline Addr realPCToFetchPC(const Addr &addr) {
- return addr;
- }
+// Instruction address compression hooks
+static inline Addr realPCToFetchPC(const Addr &addr) {
+ return addr;
+}
- static inline Addr fetchPCToRealPC(const Addr &addr) {
- return addr;
- }
+static inline Addr fetchPCToRealPC(const Addr &addr) {
+ return addr;
+}
- // the size of "fetched" instructions
- static inline size_t fetchInstSize() {
- return sizeof(MachInst);
- }
+// the size of "fetched" instructions
+static inline size_t fetchInstSize() {
+ return sizeof(MachInst);
+}
- static inline MachInst makeRegisterCopy(int dest, int src) {
- panic("makeRegisterCopy not implemented");
- return 0;
- }
+static inline MachInst makeRegisterCopy(int dest, int src) {
+ panic("makeRegisterCopy not implemented");
+ return 0;
+}
- inline void startupCPU(ThreadContext *tc, int cpuId)
- {
- tc->activate(0);
- }
+inline void startupCPU(ThreadContext *tc, int cpuId)
+{
+ tc->activate(0);
+}
- template <class XC>
- Fault
- checkFpEnableFault(XC *xc)
- {
- return NoFault;
- }
+template <class XC>
+Fault
+checkFpEnableFault(XC *xc)
+{
+ return NoFault;
+}
- static inline void
- copyRegs(ThreadContext *src, ThreadContext *dest)
- {
- panic("Copy Regs Not Implemented Yet\n");
- }
+static inline void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+ panic("Copy Regs Not Implemented Yet\n");
+}
- static inline void
- copyMiscRegs(ThreadContext *src, ThreadContext *dest)
- {
- panic("Copy Misc. Regs Not Implemented Yet\n");
- }
+static inline void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+ panic("Copy Misc. Regs Not Implemented Yet\n");
+}
- void initCPU(ThreadContext *tc, int cpuId);
-
- static inline bool
- inUserMode(ThreadContext *tc)
- {
- return (tc->readMiscRegNoEffect(MISCREG_CPSR) & 0x1f) == MODE_USER;
- }
+void initCPU(ThreadContext *tc, int cpuId);
+
+static inline bool
+inUserMode(ThreadContext *tc)
+{
+ return (tc->readMiscRegNoEffect(MISCREG_CPSR) & 0x1f) == MODE_USER;
+}
uint64_t getArgument(ThreadContext *tc, int number, bool fp);
diff --git a/src/arch/arm/vtophys.hh b/src/arch/arm/vtophys.hh
--- a/src/arch/arm/vtophys.hh
+++ b/src/arch/arm/vtophys.hh
@@ -42,17 +42,19 @@
class FunctionalPort;
namespace ArmISA {
- inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
- // User Virtual
- inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
+inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
- inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
+// User Virtual
+inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
- inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
+inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
- Addr vtophys(Addr vaddr);
- Addr vtophys(ThreadContext *tc, Addr vaddr);
+inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
+
+Addr vtophys(Addr vaddr);
+Addr vtophys(ThreadContext *tc, Addr vaddr);
+
};
#endif // __ARCH_ARM_VTOPHYS_H__
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