changeset 98101a5f7ee4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=98101a5f7ee4
description:
ARM: Begin implementing CP15
diffstat:
6 files changed, 69 insertions(+), 4 deletions(-)
src/arch/arm/insts/static_inst.cc | 1
src/arch/arm/isa/bitfields.isa | 1
src/arch/arm/isa/decoder.isa | 51 ++++++++++++++++++++++++++++++++++---
src/arch/arm/types.hh | 1
src/arch/arm/utility.cc | 16 +++++++++++
src/arch/arm/utility.hh | 3 ++
diffs (131 lines):
diff -r 06d26015e4f1 -r 98101a5f7ee4 src/arch/arm/insts/static_inst.cc
--- a/src/arch/arm/insts/static_inst.cc Tue Nov 17 18:02:08 2009 -0600
+++ b/src/arch/arm/insts/static_inst.cc Tue Nov 17 18:02:09 2009 -0600
@@ -27,6 +27,7 @@
* Authors: Stephen Hines
*/
+#include "arch/arm/faults.hh"
#include "arch/arm/insts/static_inst.hh"
#include "base/condcodes.hh"
#include "base/cprintf.hh"
diff -r 06d26015e4f1 -r 98101a5f7ee4 src/arch/arm/isa/bitfields.isa
--- a/src/arch/arm/isa/bitfields.isa Tue Nov 17 18:02:08 2009 -0600
+++ b/src/arch/arm/isa/bitfields.isa Tue Nov 17 18:02:09 2009 -0600
@@ -49,6 +49,7 @@
def bitfield OPCODE_15_12 opcode15_12;
def bitfield OPCODE_15 opcode15;
def bitfield MISC_OPCODE miscOpcode;
+def bitfield OPC2 opc2;
def bitfield OPCODE_7 opcode7;
def bitfield OPCODE_4 opcode4;
diff -r 06d26015e4f1 -r 98101a5f7ee4 src/arch/arm/isa/decoder.isa
--- a/src/arch/arm/isa/decoder.isa Tue Nov 17 18:02:08 2009 -0600
+++ b/src/arch/arm/isa/decoder.isa Tue Nov 17 18:02:09 2009 -0600
@@ -493,10 +493,53 @@
}
} // MEDIA_OPCODE (MISC_OPCODE 0x1)
} // MISC_OPCODE (CPNUM 0xA)
- 0xf: decode OPCODE_20 {
- 0: WarnUnimpl::mcr_cp15();
- 1: WarnUnimpl::mrc_cp15();
- }
+ 0xf: decode RN {
+ // Barrriers, Cache Maintence, NOPS
+ 7: decode OPCODE_23_21 {
+ 0: decode RM {
+ 0: decode OPC2 {
+ 4: decode OPCODE_20 {
+ 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
+ }
+ }
+ 1: WarnUnimpl::cp15_cache_maint();
+ 4: WarnUnimpl::cp15_par();
+ 5: decode OPC2 {
+ 0,1: WarnUnimpl::cp15_cache_maint2();
+ 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier,
IsSerializeBefore);
+ 6,7: WarnUnimpl::cp15_bp_maint();
+ }
+ 6: WarnUnimpl::cp15_cache_maint3();
+ 8: WarnUnimpl::cp15_va_to_pa();
+ 10: decode OPC2 {
+ 1,2: WarnUnimpl::cp15_cache_maint3();
+ 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier,
IsSerializeBefore);
+ 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier,
IsSerializeBefore);
+ }
+ 11: WarnUnimpl::cp15_cache_maint4();
+ 13: decode OPC2 {
+ 1: decode OPCODE_20 {
+ 0: PredOp::mcr_cp15_nop2({{ }}); // was
prefetch
+ }
+ }
+ 14: WarnUnimpl::cp15_cache_maint5();
+ } // RM
+ } // OPCODE_23_21 CR
+
+ // Thread ID and context ID registers
+ // Thread ID register needs cheaper access than miscreg
+ 13: WarnUnimpl::mcr_mrc_cp15_c7();
+
+ // All the rest
+ default: decode OPCODE_20 {
+ 0: PredOp::mcr_cp15({{
+ fault = setCp15Register(Rd, RN, OPCODE_23_21,
RM, OPC2);
+ }});
+ 1: PredOp::mrc_cp15({{
+ fault = readCp15Register(Rd, RN, OPCODE_23_21,
RM, OPC2);
+ }});
+ }
+ } // RN
} // CPNUM (OP4 == 1)
} //OPCODE_4
diff -r 06d26015e4f1 -r 98101a5f7ee4 src/arch/arm/types.hh
--- a/src/arch/arm/types.hh Tue Nov 17 18:02:08 2009 -0600
+++ b/src/arch/arm/types.hh Tue Nov 17 18:02:09 2009 -0600
@@ -58,6 +58,7 @@
Bitfield<15, 12> opcode15_12;
Bitfield<15> opcode15;
Bitfield<7, 4> miscOpcode;
+ Bitfield<7,5> opc2;
Bitfield<7> opcode7;
Bitfield<4> opcode4;
diff -r 06d26015e4f1 -r 98101a5f7ee4 src/arch/arm/utility.cc
--- a/src/arch/arm/utility.cc Tue Nov 17 18:02:08 2009 -0600
+++ b/src/arch/arm/utility.cc Tue Nov 17 18:02:09 2009 -0600
@@ -57,4 +57,20 @@
#endif
}
+Fault
+setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2)
+{
+ return new UnimpFault(csprintf("MCR CP15: CRn: %d opc1: %d CRm: %d opc1:
%d\n",
+ CRn, opc1, CRm, opc2));
}
+
+Fault
+readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2)
+{
+ return new UnimpFault(csprintf("MRC CP15: CRn: %d opc1: %d CRm: %d opc1:
%d\n",
+ CRn, opc1, CRm, opc2));
+
+}
+
+
+}
diff -r 06d26015e4f1 -r 98101a5f7ee4 src/arch/arm/utility.hh
--- a/src/arch/arm/utility.hh Tue Nov 17 18:02:08 2009 -0600
+++ b/src/arch/arm/utility.hh Tue Nov 17 18:02:09 2009 -0600
@@ -135,6 +135,9 @@
}
uint64_t getArgument(ThreadContext *tc, int number, bool fp);
+
+Fault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
+Fault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
};
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