Hi Tim,
It looks like you lost the initialization of isUncacheable... is that safe?
> diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
> --- a/src/cpu/base_dyn_inst.hh
> +++ b/src/cpu/base_dyn_inst.hh
> @@ -861,29 +871,14 @@
> Request *req = new Request(asid, addr, sizeof(T), flags, this->PC,
> thread->contextId(), threadNumber);
>
> - fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read);
> + initiateTranslation(req, NULL, BaseTLB::Read);
>
> - if (req->isUncacheable())
> - isUncacheable = true;
> + effAddr = req->getVaddr();
> + effAddrValid = true;
> + if (fault == NoFault) {
> + cpu->read(req, data, lqIdx);
> + } else {
>
Actually I'm not sure why we need that variable, and don't just have
BaseDynInst::uncacheable() call req->isUncacheable() directly (unless
there are times we call it when we don't have a req, but then how do
we know the right answer?).
Also I'd suggest just folding this patch in with your last patch that
fixes up TimingSimpleCPU too, basically getting there in one step
instead of two.
Thanks for all the great work!
Steve
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