[m5-dev] [PATCH 05 of 41] ruby: Calculate system total memory capacity in Python

[Brad Beckmann]

# HG changeset patch
# User Steve Reinhardt <steve.reinha...@amd.com>
# Date 1263536243 28800
# Node ID 9e35210428f8c5c7fd2bec745d4b4514923add15
# Parent  66e2254601b93184d109026173b22beafed99693
ruby: Calculate system total memory capacity in Python
rather than in RubySystem object.

diff -r 66e2254601b9 -r 9e35210428f8 configs/example/memtest-ruby.py
--- a/configs/example/memtest-ruby.py   Thu Jan 14 22:17:23 2010 -0800
+++ b/configs/example/memtest-ruby.py   Thu Jan 14 22:17:23 2010 -0800
@@ -127,10 +127,14 @@
 network = SimpleNetwork(topology = makeCrossbar(l1_cntrl_nodes + \
                                                 dir_cntrl_nodes))
 
+mem_size_mb = sum([int(dir_cntrl.directory.size_mb) \
+                   for dir_cntrl in dir_cntrl_nodes])
+
 system.ruby = RubySystem(network = network,
                          profiler = RubyProfiler(),
                          tracer = RubyTracer(),
-                         debug = RubyDebug())
+                         debug = RubyDebug(),
+                         mem_size_mb = mem_size_mb)
 
 
 # -----------------------
diff -r 66e2254601b9 -r 9e35210428f8 src/mem/ruby/system/RubySystem.py
--- a/src/mem/ruby/system/RubySystem.py Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/system/RubySystem.py Thu Jan 14 22:17:23 2010 -0800
@@ -11,6 +11,7 @@
     freq_mhz = Param.Int(3000, "default frequency for the system");
     block_size_bytes = Param.Int(64,
         "default cache block size; must be a power of two");
+    mem_size_mb = Param.Int("");
     network = Param.RubyNetwork("")
     debug = Param.RubyDebug("the default debug object")
     profiler = Param.RubyProfiler("");
diff -r 66e2254601b9 -r 9e35210428f8 src/mem/ruby/system/System.cc
--- a/src/mem/ruby/system/System.cc     Thu Jan 14 22:17:23 2010 -0800
+++ b/src/mem/ruby/system/System.cc     Thu Jan 14 22:17:23 2010 -0800
@@ -94,9 +94,14 @@
     m_randomization = p->randomization;
     m_tech_nm = p->tech_nm;
     m_freq_mhz = p->freq_mhz;
+
     m_block_size_bytes = p->block_size_bytes;
     assert(is_power_of_2(m_block_size_bytes));
     m_block_size_bits = log_int(m_block_size_bytes);
+
+    m_memory_size_bytes = (uint64_t)p->mem_size_mb * 1024 * 1024;
+    m_memory_size_bits = log_int(m_memory_size_bytes);
+
     m_network_ptr = p->network;
     g_debug_ptr = p->debug;
     m_profiler_ptr = p->profiler;
@@ -104,23 +109,12 @@
 
     g_system_ptr = this;
     m_mem_vec_ptr = new MemoryVector;
+    m_mem_vec_ptr->setSize(m_memory_size_bytes);
 }
 
 
 void RubySystem::init()
 {
-  // calculate system-wide parameters
-  m_memory_size_bytes = 0;
-  DirectoryMemory* prev = NULL;
-  for (map< string, DirectoryMemory*>::const_iterator it = 
m_directories.begin();
-       it != m_directories.end(); it++) {
-    if (prev != NULL)
-      assert((*it).second->getSize() == prev->getSize()); // must be equal for 
proper address mapping
-    m_memory_size_bytes += (*it).second->getSize();
-    prev = (*it).second;
-  }
-  m_mem_vec_ptr->setSize(m_memory_size_bytes);
-  m_memory_size_bits = log_int(m_memory_size_bytes);
 }
 
 

_______________________________________________
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev