Just about RMW sequence in real CPU. It is needed when CPU writes less then
data bus size and there is ECC. CPU needs to read complete word or double
word, modify appropriate bytes, recalculate ECC bits and then write it back.
Or, memory system must do RMW in same way, but it is not possible to do
partial modification of word or double word "in place". And for MIPS it
depends is access to cached or uncached memory region (kseg1/disabled
caching in TLB entry or normal cached access). Same applies to caches if it
have ECC (probably L2 or L3, L1 highly unlikely), but explicit partial
load/stores are not very common and cached byte/half word stores goes to L1
caches which usually have just parity which can be updated in the flight.
----- Original Message -----
From: "Steve Reinhardt" <[email protected]>
To: "M5 Developer List" <[email protected]>
Sent: 20. N~?�?1Nf?�N� 2010 2:31
Subject: Re: [m5-dev] MIPS o3 unaligned store error
In hardware it's pretty easy to do per-byte enables if you need to;
much simpler than doing a read-modify-write sequence. The only reason
I can imagine that they wouldn't do it that way is if they already had
to do an RMW for some other instructions and so they piggybacked on
that. I don't know of any MIPS instructions that would require RMW
though (particularly since MIPS uses LL/SC for atomic ops, which is
the main reason you'd want RMW).
Have we discussed doing 3-byte memory ops on the list before? It's
clear it would require some new functionality at the read()/write()
ExecContext interface, but that seems like a worthwhile addition to
me.
Steve
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