Those are good points... thanks for bringing them up. From a software engineering perspective at least, I think the details of ECC should be internal to the cache or memory device model, so the external Request/Packet interface should still allow partial accesses. You're right that if you want to enable these instructions for uncached accesses then you need to push something like byte enables all the way across the I/O bus; I vaguely recall that we discussed doing this for Alpha (to support write-combining on uncached writes?) but I don't recall that we actually did it.
Steve On Wed, Jan 20, 2010 at 4:57 AM, Radivoje Vasiljevic <[email protected]> wrote: > Just about RMW sequence in real CPU. It is needed when CPU writes less then > data bus size and there is ECC. CPU needs to read complete word or double > word, modify appropriate bytes, recalculate ECC bits and then write it back. > Or, memory system must do RMW in same way, but it is not possible to do > partial modification of word or double word "in place". And for MIPS it > depends is access to cached or uncached memory region (kseg1/disabled > caching in TLB entry or normal cached access). Same applies to caches if it > have ECC (probably L2 or L3, L1 highly unlikely), but explicit partial > load/stores are not very common and cached byte/half word stores goes to L1 > caches which usually have just parity which can be updated in the flight. > > ----- Original Message ----- From: "Steve Reinhardt" <[email protected]> > To: "M5 Developer List" <[email protected]> > Sent: 20. N~?°?1Nf?°N€ 2010 2:31 > Subject: Re: [m5-dev] MIPS o3 unaligned store error > > > >> In hardware it's pretty easy to do per-byte enables if you need to; >> much simpler than doing a read-modify-write sequence. The only reason >> I can imagine that they wouldn't do it that way is if they already had >> to do an RMW for some other instructions and so they piggybacked on >> that. I don't know of any MIPS instructions that would require RMW >> though (particularly since MIPS uses LL/SC for atomic ops, which is >> the main reason you'd want RMW). > >> Have we discussed doing 3-byte memory ops on the list before? It's >> clear it would require some new functionality at the read()/write() >> ExecContext interface, but that seems like a worthwhile addition to >> me. > >> Steve > > > > > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
