changeset 0cf7d56ab5d7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0cf7d56ab5d7
description:
inorder: init internal debug cpu counters
- cpuEventNum
- resReqCount
diffstat:
4 files changed, 128 insertions(+), 58 deletions(-)
src/cpu/inorder/cpu.cc | 60 ++++++++++++++++++++++++++++++-------------
src/cpu/inorder/cpu.hh | 32 +++++++++++++++++-----
src/cpu/inorder/resource.cc | 54 +++++++++++++++++++++++++++++++++-----
src/cpu/inorder/resource.hh | 40 +++++++++-------------------
diffs (truncated from 428 to 300 lines):
diff -r 5bd33f7c26ea -r 0cf7d56ab5d7 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Fri Jan 29 20:29:40 2010 -0800
+++ b/src/cpu/inorder/cpu.cc Sun Jan 31 17:18:15 2010 -0500
@@ -115,7 +115,8 @@
cpu->activateThread(tid);
break;
- //@TODO: Consider Implementing "Suspend Thread" as Separate from
Deallocate
+ //@TODO: Consider Implementing "Suspend Thread" as Separate from
+ //Deallocate
case SuspendThread: // Suspend & Deallocate are same for now.
//cpu->suspendThread(tid);
//break;
@@ -145,11 +146,14 @@
default:
fatal("Unrecognized Event Type %d", cpuEventType);
+
}
-
+
cpu->cpuEventRemoveList.push(this);
}
+
+
const char *
InOrderCPU::CPUEvent::description()
{
@@ -185,6 +189,10 @@
system(params->system),
physmem(system->physmem),
#endif // FULL_SYSTEM
+#ifdef DEBUG
+ cpuEventNum(0),
+ resReqCount(0),
+#endif // DEBUG
switchCount(0),
deferRegistration(false/*params->deferRegistration*/),
stageTracing(params->stageTracing),
@@ -301,7 +309,7 @@
// Define dummy instructions and resource requests to be used.
DynInstPtr dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0);
- dummyReq = new ResourceRequest(NULL, NULL, 0, 0, 0, 0);
+ dummyReq = new ResourceRequest(resPool->getResource(0), NULL, 0, 0, 0, 0);
// Reset CPU to reset state.
#if FULL_SYSTEM
@@ -322,6 +330,13 @@
/* Register the Resource Pool's stats here.*/
resPool->regStats();
+#ifdef DEBUG
+ maxResReqCount
+ .name(name() + ".maxResReqCount")
+ .desc("Maximum number of live resource requests in CPU")
+ .prereq(maxResReqCount);
+#endif
+
/* Register any of the InOrderCPU's stats here.*/
timesIdled
.name(name() + ".timesIdled")
@@ -342,7 +357,7 @@
smtCycles
.name(name() + ".smtCycles")
- .desc("Total number of cycles that the CPU was simultaneous
multithreading.(SMT)");
+ .desc("Total number of cycles that the CPU was in SMT-mode");
committedInsts
.init(numThreads)
@@ -435,7 +450,8 @@
//Tick next_tick = curTick + cycles(1);
//tickEvent.schedule(next_tick);
mainEventQueue.schedule(&tickEvent, nextCycle(curTick + 1));
- DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
nextCycle(curTick + 1));
+ DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
+ nextCycle(curTick + 1));
}
}
@@ -640,8 +656,8 @@
InOrderCPU::addToCurrentThreads(ThreadID tid)
{
if (!isThreadInCPU(tid)) {
- DPRINTF(InOrderCPU, "Adding Thread %i to current threads list in
CPU.\n",
- tid);
+ DPRINTF(InOrderCPU, "Adding Thread %i to current threads list in CPU."
+ "\n", tid);
currentThreads.push_back(tid);
}
}
@@ -1002,9 +1018,11 @@
tid = TheISA::getTargetThread(tcBase(tid));
}
- if (reg_idx < FP_Base_DepTag) { // Integer Register File
+ if (reg_idx < FP_Base_DepTag) {
+ // Integer Register File
return readIntReg(reg_idx, tid);
- } else if (reg_idx < Ctrl_Base_DepTag) { // Float Register File
+ } else if (reg_idx < Ctrl_Base_DepTag) {
+ // Float Register File
reg_idx -= FP_Base_DepTag;
return readFloatRegBits(reg_idx, tid);
} else {
@@ -1070,9 +1088,12 @@
void
InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
{
- // Set the CPU's PCs - This contributes to the precise state of the CPU
which can be used
- // when restoring a thread to the CPU after a fork or after an exception
- // @TODO: Set-Up Grad-Info/Committed-Info to let ThreadState know if it's
a branch or not
+ // Set the CPU's PCs - This contributes to the precise state of the CPU
+ // which can be used when restoring a thread to the CPU after a fork or
+ // after an exception
+ // =================
+ // @TODO: Set-Up Grad-Info/Committed-Info to let ThreadState know if
+ // it's a branch or not
setPC(inst->readPC(), tid);
setNextPC(inst->readNextPC(), tid);
setNextNPC(inst->readNextNPC(), tid);
@@ -1112,7 +1133,8 @@
// Broadcast to other resources an instruction
// has been completed
- resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
tid);
+ resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
+ tid);
// Finally, remove instruction from CPU
removeInst(inst);
@@ -1380,7 +1402,8 @@
{
//@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
// you want to run w/out caches?
- CacheUnit *cache_res =
dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
+ CacheUnit *cache_res =
+ dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
return cache_res->read(inst, addr, data, flags);
}
@@ -1483,14 +1506,16 @@
template<>
Fault
-InOrderCPU::write(DynInstPtr inst, double data, Addr addr, unsigned flags,
uint64_t *res)
+InOrderCPU::write(DynInstPtr inst, double data, Addr addr, unsigned flags,
+ uint64_t *res)
{
return write(inst, *(uint64_t*)&data, addr, flags, res);
}
template<>
Fault
-InOrderCPU::write(DynInstPtr inst, float data, Addr addr, unsigned flags,
uint64_t *res)
+InOrderCPU::write(DynInstPtr inst, float data, Addr addr, unsigned flags,
+ uint64_t *res)
{
return write(inst, *(uint32_t*)&data, addr, flags, res);
}
@@ -1498,7 +1523,8 @@
template<>
Fault
-InOrderCPU::write(DynInstPtr inst, int32_t data, Addr addr, unsigned flags,
uint64_t *res)
+InOrderCPU::write(DynInstPtr inst, int32_t data, Addr addr, unsigned flags,
+ uint64_t *res)
{
return write(inst, (uint32_t)data, addr, flags, res);
}
diff -r 5bd33f7c26ea -r 0cf7d56ab5d7 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Fri Jan 29 20:29:40 2010 -0800
+++ b/src/cpu/inorder/cpu.hh Sun Jan 31 17:18:15 2010 -0500
@@ -144,9 +144,11 @@
void scheduleTickEvent(int delay)
{
if (tickEvent.squashed())
- mainEventQueue.reschedule(&tickEvent, nextCycle(curTick +
ticks(delay)));
+ mainEventQueue.reschedule(&tickEvent,
+ nextCycle(curTick + ticks(delay)));
else if (!tickEvent.scheduled())
- mainEventQueue.schedule(&tickEvent, nextCycle(curTick +
ticks(delay)));
+ mainEventQueue.schedule(&tickEvent,
+ nextCycle(curTick + ticks(delay)));
}
/** Unschedule tick event, regardless of its current state. */
@@ -228,7 +230,8 @@
/** Interface between the CPU and CPU resources. */
ResourcePool *resPool;
- /** Instruction used to signify that there is no *real* instruction in
buffer slot */
+ /** Instruction used to signify that there is no *real* instruction in
+ buffer slot */
DynInstPtr dummyBufferInst;
/** Used by resources to signify a denied access to a resource. */
@@ -420,7 +423,11 @@
/** Get & Update Next Event Number */
InstSeqNum getNextEventNum()
{
+#ifdef DEBUG
return cpuEventNum++;
+#else
+ return 0;
+#endif
}
/** Register file accessors */
@@ -550,8 +557,8 @@
*/
std::queue<ListIt> removeList;
- /** List of all the resource requests that will be removed at the end of
this
- * cycle.
+ /** List of all the resource requests that will be removed at the end
+ * of this cycle.
*/
std::queue<ResourceRequest*> reqRemoveList;
@@ -632,8 +639,12 @@
// LL/SC debug functionality
unsigned stCondFails;
- unsigned readStCondFailures() { return stCondFails; }
- unsigned setStCondFailures(unsigned st_fails) { return stCondFails =
st_fails; }
+
+ unsigned readStCondFailures()
+ { return stCondFails; }
+
+ unsigned setStCondFailures(unsigned st_fails)
+ { return stCondFails = st_fails; }
/** Returns a pointer to a thread context. */
ThreadContext *tcBase(ThreadID tid = 0)
@@ -663,9 +674,16 @@
/** The global sequence number counter. */
InstSeqNum globalSeqNum[ThePipeline::MaxThreads];
+#ifdef DEBUG
/** The global event number counter. */
InstSeqNum cpuEventNum;
+ /** Number of resource requests active in CPU **/
+ unsigned resReqCount;
+
+ Stats::Scalar maxResReqCount;
+#endif
+
/** Counter of how many stages have completed switching out. */
int switchCount;
diff -r 5bd33f7c26ea -r 0cf7d56ab5d7 src/cpu/inorder/resource.cc
--- a/src/cpu/inorder/resource.cc Fri Jan 29 20:29:40 2010 -0800
+++ b/src/cpu/inorder/resource.cc Sun Jan 31 17:18:15 2010 -0500
@@ -80,7 +80,8 @@
{
instReqsProcessed
.name(name() + ".instReqsProcessed")
- .desc("Number of Instructions Requests that completed in this
resource.");
+ .desc("Number of Instructions Requests that completed in "
+ "this resource.");
}
int
@@ -98,7 +99,8 @@
void
Resource::freeSlot(int slot_idx)
{
- DPRINTF(RefCount, "Removing [tid:%i] [sn:%i]'s request from resource
[slot:%i].\n",
+ DPRINTF(RefCount, "Removing [tid:%i] [sn:%i]'s request from resource "
+ "[slot:%i].\n",
reqMap[slot_idx]->inst->readTid(),
reqMap[slot_idx]->inst->seqNum,
slot_idx);
@@ -159,7 +161,8 @@
while (map_it != map_end) {
if ((*map_it).second) {
- DPRINTF(Resource, "Currently Serving request from: [tid:%i]
[sn:%i].\n",
+ DPRINTF(Resource, "Currently Serving request from: "
+ "[tid:%i] [sn:%i].\n",
(*map_it).second->getInst()->readTid(),
(*map_it).second->getInst()->seqNum);
}
@@ -202,10 +205,12 @@
inst_req = getRequest(inst, stage_num, id, slot_num, cmd);
if (inst->staticInst) {
- DPRINTF(Resource, "[tid:%i]: [sn:%i] requesting this
resource.\n",
+ DPRINTF(Resource, "[tid:%i]: [sn:%i] requesting this "
+ "resource.\n",
inst->readTid(), inst->seqNum);
} else {
- DPRINTF(Resource, "[tid:%i]: instruction requesting this
resource.\n",
+ DPRINTF(Resource, "[tid:%i]: instruction requesting this "
+ "resource.\n",
inst->readTid());
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