changeset 6d7f25432d1c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6d7f25432d1c
description:
configs/inorder: add options for switch-on-miss to inorder cpu
diffstat:
3 files changed, 24 insertions(+), 2 deletions(-)
src/cpu/inorder/InOrderCPU.py | 5 +++++
src/cpu/inorder/cpu.cc | 11 ++++++++++-
src/cpu/inorder/cpu.hh | 10 +++++++++-
diffs (74 lines):
diff -r 0cf7d56ab5d7 -r 6d7f25432d1c src/cpu/inorder/InOrderCPU.py
--- a/src/cpu/inorder/InOrderCPU.py Sun Jan 31 17:18:15 2010 -0500
+++ b/src/cpu/inorder/InOrderCPU.py Sun Jan 31 18:25:13 2010 -0500
@@ -30,10 +30,15 @@
from m5.proxy import *
from BaseCPU import BaseCPU
+class ThreadModel(Enum):
+ vals = ['Single', 'SMT', 'SwitchOnCacheMiss']
+
class InOrderCPU(BaseCPU):
type = 'InOrderCPU'
activity = Param.Unsigned(0, "Initial count")
+ threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE
only)")
+
cachePorts = Param.Unsigned(2, "Cache Ports")
stageWidth = Param.Unsigned(1, "Stage width")
diff -r 0cf7d56ab5d7 -r 6d7f25432d1c src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Sun Jan 31 17:18:15 2010 -0500
+++ b/src/cpu/inorder/cpu.cc Sun Jan 31 18:25:13 2010 -0500
@@ -197,7 +197,7 @@
deferRegistration(false/*params->deferRegistration*/),
stageTracing(params->stageTracing),
numVirtProcs(1)
-{
+{
ThreadID active_threads;
cpu_params = params;
@@ -216,6 +216,15 @@
"in your InOrder implementation or "
"edit your workload size.");
}
+
+ if (active_threads > 1) {
+ threadModel = (InOrderCPU::ThreadModel) params->threadModel;
+ } else {
+ threadModel = Single;
+ }
+
+
+
#endif
// Bind the fetch & data ports from the resource pool.
diff -r 0cf7d56ab5d7 -r 6d7f25432d1c src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Sun Jan 31 17:18:15 2010 -0500
+++ b/src/cpu/inorder/cpu.hh Sun Jan 31 18:25:13 2010 -0500
@@ -100,6 +100,15 @@
/** Type of core that this is */
std::string coreType;
+ // Only need for SE MODE
+ enum ThreadModel {
+ Single,
+ SMT,
+ SwitchOnCacheMiss
+ };
+
+ ThreadModel threadModel;
+
int readCpuId() { return cpu_id; }
void setCpuId(int val) { cpu_id = val; }
@@ -117,7 +126,6 @@
/** Overall CPU status. */
Status _status;
-
private:
/** Define TickEvent for the CPU */
class TickEvent : public Event
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
