changeset 7eb151d3881f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7eb151d3881f
description:
inorder: enforce stage bandwidth
each stage keeps track of insts_processed on a per_thread basis but we
should
be keeping that on a total basis inorder to enforce stage width limits
diffstat:
3 files changed, 28 insertions(+), 12 deletions(-)
src/cpu/inorder/first_stage.cc | 11 ++++++++---
src/cpu/inorder/pipeline_stage.cc | 22 ++++++++++++++--------
src/cpu/inorder/pipeline_stage.hh | 7 ++++++-
diffs (115 lines):
diff -r 862f3d824be7 -r 7eb151d3881f src/cpu/inorder/first_stage.cc
--- a/src/cpu/inorder/first_stage.cc Sun Jan 31 18:28:12 2010 -0500
+++ b/src/cpu/inorder/first_stage.cc Sun Jan 31 18:28:31 2010 -0500
@@ -175,9 +175,14 @@
ThePipeline::createFrontEndSchedule(inst);
}
- // Don't let instruction pass to next stage if it hasnt completed
- // all of it's requests for this stage.
- all_reqs_completed = processInstSchedule(inst);
+ int reqs_processed = 0;
+ all_reqs_completed = processInstSchedule(inst, reqs_processed);
+
+ // If the instruction isnt squashed & we've completed one request
+ // Then we can officially count this instruction toward the stage's
+ // bandwidth count
+ if (reqs_processed > 0)
+ instsProcessed++;
if (!all_reqs_completed) {
if (new_inst) {
diff -r 862f3d824be7 -r 7eb151d3881f src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Sun Jan 31 18:28:12 2010 -0500
+++ b/src/cpu/inorder/pipeline_stage.cc Sun Jan 31 18:28:31 2010 -0500
@@ -726,8 +726,10 @@
nextStage->size = 0;
toNextStageIndex = 0;
+
+ sortInsts();
- sortInsts();
+ instsProcessed = 0;
processStage(status_change);
@@ -873,10 +875,8 @@
DynInstPtr inst;
bool last_req_completed = true;
- int insts_processed = 0;
-
while (insts_available > 0 &&
- insts_processed < stageWidth &&
+ instsProcessed < stageWidth &&
(!nextStageValid || canSendInstToStage(stageNum+1)) &&
last_req_completed) {
assert(!insts_to_stage.empty());
@@ -901,8 +901,14 @@
continue;
}
+ int reqs_processed = 0;
+ last_req_completed = processInstSchedule(inst, reqs_processed);
- last_req_completed = processInstSchedule(inst);
+ // If the instruction isnt squashed & we've completed one request
+ // Then we can officially count this instruction toward the stage's
+ // bandwidth count
+ if (reqs_processed > 0)
+ instsProcessed++;
// Don't let instruction pass to next stage if it hasnt completed
// all of it's requests for this stage.
@@ -916,8 +922,6 @@
break;
}
- insts_processed++;
-
insts_to_stage.pop();
//++stageProcessedInsts;
@@ -938,7 +942,7 @@
}
bool
-PipelineStage::processInstSchedule(DynInstPtr inst)
+PipelineStage::processInstSchedule(DynInstPtr inst,int &reqs_processed)
{
bool last_req_completed = true;
ThreadID tid = inst->readTid();
@@ -966,6 +970,8 @@
panic("%i: encountered %s fault!\n",
curTick, req->fault->name());
}
+
+ reqs_processed++;
} else {
DPRINTF(InOrderStage, "[tid:%i]: [sn:%i] request to %s failed."
"\n", tid, inst->seqNum, cpu->resPool->name(res_num));
diff -r 862f3d824be7 -r 7eb151d3881f src/cpu/inorder/pipeline_stage.hh
--- a/src/cpu/inorder/pipeline_stage.hh Sun Jan 31 18:28:12 2010 -0500
+++ b/src/cpu/inorder/pipeline_stage.hh Sun Jan 31 18:28:31 2010 -0500
@@ -178,7 +178,7 @@
virtual void processInsts(ThreadID tid);
/** Process all resources on an instruction's resource schedule */
- virtual bool processInstSchedule(DynInstPtr inst);
+ virtual bool processInstSchedule(DynInstPtr inst, int &reqs_processed);
/** Is there room in the next stage buffer for this instruction? */
virtual bool canSendInstToStage(unsigned stage_num);
@@ -270,6 +270,11 @@
std::vector<DynInstPtr> switchedOutBuffer;
std::vector<bool> switchedOutValid;
+ /** Instructions that we've processed this tick
+ * NOTE: "Processed" means completed at least 1 instruction request
+ */
+ unsigned instsProcessed;
+
/** Queue of all instructions coming from previous stage on this cycle. */
std::queue<DynInstPtr> insts[ThePipeline::MaxThreads];
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