changeset 5fe4afb992f5 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=5fe4afb992f5 description: m5: Added PROTOCOL default for regress fix
diffstat: 11 files changed, 10 insertions(+), 1 deletion(-) build_opts/ALPHA_FS | 1 + build_opts/ALPHA_SE | 1 + build_opts/ARM_FS | 1 + build_opts/ARM_SE | 1 + build_opts/MIPS_FS | 1 + build_opts/MIPS_SE | 1 - build_opts/POWER_SE | 1 + build_opts/SPARC_FS | 1 + build_opts/SPARC_SE | 1 + build_opts/X86_FS | 1 + build_opts/X86_SE | 1 + diffs (89 lines): diff -r 5bd33f7c26ea -r 5fe4afb992f5 build_opts/ALPHA_FS --- a/build_opts/ALPHA_FS Fri Jan 29 20:29:40 2010 -0800 +++ b/build_opts/ALPHA_FS Sun Jan 31 22:21:01 2010 -0800 @@ -1,3 +1,4 @@ TARGET_ISA = 'alpha' FULL_SYSTEM = 1 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' +PROTOCOL = 'MI_example' diff -r 5bd33f7c26ea -r 5fe4afb992f5 build_opts/ALPHA_SE --- a/build_opts/ALPHA_SE Fri Jan 29 20:29:40 2010 -0800 +++ b/build_opts/ALPHA_SE Sun Jan 31 22:21:01 2010 -0800 @@ -1,3 +1,4 @@ FULL_SYSTEM = 0 SS_COMPATIBLE_FP = 1 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' +PROTOCOL = 'MI_example' diff -r 5bd33f7c26ea -r 5fe4afb992f5 build_opts/ARM_FS --- a/build_opts/ARM_FS Fri Jan 29 20:29:40 2010 -0800 +++ b/build_opts/ARM_FS Sun Jan 31 22:21:01 2010 -0800 @@ -1,3 +1,4 @@ TARGET_ISA = 'arm' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' FULL_SYSTEM = 1 +PROTOCOL = 'MI_example' diff -r 5bd33f7c26ea -r 5fe4afb992f5 build_opts/ARM_SE --- a/build_opts/ARM_SE Fri Jan 29 20:29:40 2010 -0800 +++ b/build_opts/ARM_SE Sun Jan 31 22:21:01 2010 -0800 @@ -1,3 +1,4 @@ TARGET_ISA = 'arm' FULL_SYSTEM = 0 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' +PROTOCOL = 'MI_example' diff -r 5bd33f7c26ea -r 5fe4afb992f5 build_opts/MIPS_FS --- a/build_opts/MIPS_FS Fri Jan 29 20:29:40 2010 -0800 +++ b/build_opts/MIPS_FS Sun Jan 31 22:21:01 2010 -0800 @@ -1,2 +1,3 @@ TARGET_ISA = 'mips' FULL_SYSTEM = 1 +PROTOCOL = 'MI_example' diff -r 5bd33f7c26ea -r 5fe4afb992f5 build_opts/MIPS_SE --- a/build_opts/MIPS_SE Fri Jan 29 20:29:40 2010 -0800 +++ b/build_opts/MIPS_SE Sun Jan 31 22:21:01 2010 -0800 @@ -1,3 +1,4 @@ TARGET_ISA = 'mips' FULL_SYSTEM = 0 -CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' \ No newline at end of file +CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' +PROTOCOL = 'MI_example' diff -r 5bd33f7c26ea -r 5fe4afb992f5 build_opts/POWER_SE --- a/build_opts/POWER_SE Fri Jan 29 20:29:40 2010 -0800 +++ b/build_opts/POWER_SE Sun Jan 31 22:21:01 2010 -0800 @@ -1,3 +1,4 @@ TARGET_ISA = 'power' FULL_SYSTEM = 0 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' +PROTOCOL = 'MI_example' diff -r 5bd33f7c26ea -r 5fe4afb992f5 build_opts/SPARC_FS --- a/build_opts/SPARC_FS Fri Jan 29 20:29:40 2010 -0800 +++ b/build_opts/SPARC_FS Sun Jan 31 22:21:01 2010 -0800 @@ -1,3 +1,4 @@ TARGET_ISA = 'sparc' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' FULL_SYSTEM = 1 +PROTOCOL = 'MI_example' diff -r 5bd33f7c26ea -r 5fe4afb992f5 build_opts/SPARC_SE --- a/build_opts/SPARC_SE Fri Jan 29 20:29:40 2010 -0800 +++ b/build_opts/SPARC_SE Sun Jan 31 22:21:01 2010 -0800 @@ -1,3 +1,4 @@ TARGET_ISA = 'sparc' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' FULL_SYSTEM = 0 +PROTOCOL = 'MI_example' diff -r 5bd33f7c26ea -r 5fe4afb992f5 build_opts/X86_FS --- a/build_opts/X86_FS Fri Jan 29 20:29:40 2010 -0800 +++ b/build_opts/X86_FS Sun Jan 31 22:21:01 2010 -0800 @@ -1,3 +1,4 @@ TARGET_ISA = 'x86' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' FULL_SYSTEM = 1 +PROTOCOL = 'MI_example' diff -r 5bd33f7c26ea -r 5fe4afb992f5 build_opts/X86_SE --- a/build_opts/X86_SE Fri Jan 29 20:29:40 2010 -0800 +++ b/build_opts/X86_SE Sun Jan 31 22:21:01 2010 -0800 @@ -1,3 +1,4 @@ TARGET_ISA = 'x86' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' FULL_SYSTEM = 0 +PROTOCOL = 'MI_example' _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
