changeset 6531ddc70176 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6531ddc70176
description:
m5: merge inorder updates
diffstat:
25 files changed, 1627 insertions(+), 1572 deletions(-)
src/arch/alpha/isa/mem.isa | 6
src/arch/arm/isa/formats/mem.isa | 2
src/arch/mips/isa/formats/mem.isa | 8
src/arch/mips/isa/formats/util.isa | 3
src/arch/power/isa/formats/mem.isa | 2
src/arch/power/isa/formats/util.isa | 3
src/cpu/inorder/resources/cache_unit.cc | 9
src/cpu/simple/atomic.cc | 15
src/cpu/simple/base.cc | 21
src/cpu/simple/base.hh | 12
src/cpu/simple/timing.cc | 30
src/cpu/translation.hh | 64 +
src/mem/ruby/profiler/AccessTraceForAddress.cc | 135 +--
src/mem/ruby/profiler/AccessTraceForAddress.hh | 108 +-
src/mem/ruby/profiler/AddressProfiler.cc | 484 ++++++------
src/mem/ruby/profiler/AddressProfiler.hh | 117 +-
src/mem/ruby/profiler/CacheProfiler.cc | 163 ++--
src/mem/ruby/profiler/CacheProfiler.hh | 90 --
src/mem/ruby/profiler/MemCntrlProfiler.cc | 197 ++--
src/mem/ruby/profiler/MemCntrlProfiler.hh | 133 +--
src/mem/ruby/profiler/Profiler.cc | 965 ++++++++++++------------
src/mem/ruby/profiler/Profiler.hh | 259 +++---
src/mem/ruby/profiler/StoreTrace.cc | 183 ++--
src/mem/ruby/profiler/StoreTrace.hh | 112 +-
util/regress | 78 +
diffs (truncated from 4168 to 300 lines):
diff -r d4921c2e136b -r 6531ddc70176 src/arch/alpha/isa/mem.isa
--- a/src/arch/alpha/isa/mem.isa Sat Mar 27 02:21:22 2010 -0400
+++ b/src/arch/alpha/isa/mem.isa Sat Mar 27 02:23:00 2010 -0400
@@ -275,7 +275,6 @@
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
}
if (fault == NoFault) {
@@ -310,7 +309,6 @@
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, &write_result);
- if (traceData) { traceData->setData(Mem); }
}
if (fault == NoFault) {
@@ -344,7 +342,6 @@
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
}
return fault;
@@ -478,9 +475,6 @@
mem_flags = makeList(mem_flags)
inst_flags = makeList(inst_flags)
- # add hook to get effective addresses into execution trace output.
- ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
-
# Some CPU models execute the memory operation as an atomic unit,
# while others want to separate them into an effective address
# computation and a memory access operation. As a result, we need
diff -r d4921c2e136b -r 6531ddc70176 src/arch/arm/isa/formats/mem.isa
--- a/src/arch/arm/isa/formats/mem.isa Sat Mar 27 02:21:22 2010 -0400
+++ b/src/arch/arm/isa/formats/mem.isa Sat Mar 27 02:23:00 2010 -0400
@@ -172,7 +172,6 @@
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
}
if (fault == NoFault) {
@@ -204,7 +203,6 @@
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
}
// Need to write back any potential address register update
diff -r d4921c2e136b -r 6531ddc70176 src/arch/mips/isa/formats/mem.isa
--- a/src/arch/mips/isa/formats/mem.isa Sat Mar 27 02:21:22 2010 -0400
+++ b/src/arch/mips/isa/formats/mem.isa Sat Mar 27 02:23:00 2010 -0400
@@ -305,7 +305,6 @@
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
}
if (fault == NoFault) {
@@ -342,7 +341,6 @@
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
}
if (fault == NoFault) {
@@ -377,7 +375,6 @@
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, &write_result);
- if (traceData) { traceData->setData(Mem); }
}
if (fault == NoFault) {
@@ -411,7 +408,6 @@
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
}
return fault;
@@ -435,8 +431,6 @@
if (fault == NoFault) {
%(op_wb)s;
-
- if (traceData) { traceData->setData(getMemData(xc, pkt)); }
}
return fault;
@@ -459,8 +453,6 @@
if (fault == NoFault) {
%(op_wb)s;
-
- if (traceData) { traceData->setData(getMemData(xc, pkt)); }
}
return fault;
diff -r d4921c2e136b -r 6531ddc70176 src/arch/mips/isa/formats/util.isa
--- a/src/arch/mips/isa/formats/util.isa Sat Mar 27 02:21:22 2010 -0400
+++ b/src/arch/mips/isa/formats/util.isa Sat Mar 27 02:23:00 2010 -0400
@@ -38,9 +38,6 @@
mem_flags = makeList(mem_flags)
inst_flags = makeList(inst_flags)
- # add hook to get effective addresses into execution trace output.
- ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
-
# Some CPU models execute the memory operation as an atomic unit,
# while others want to separate them into an effective address
# computation and a memory access operation. As a result, we need
diff -r d4921c2e136b -r 6531ddc70176 src/arch/power/isa/formats/mem.isa
--- a/src/arch/power/isa/formats/mem.isa Sat Mar 27 02:21:22 2010 -0400
+++ b/src/arch/power/isa/formats/mem.isa Sat Mar 27 02:23:00 2010 -0400
@@ -166,7 +166,6 @@
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
}
if (fault == NoFault) {
@@ -196,7 +195,6 @@
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
}
// Need to write back any potential address register update
diff -r d4921c2e136b -r 6531ddc70176 src/arch/power/isa/formats/util.isa
--- a/src/arch/power/isa/formats/util.isa Sat Mar 27 02:21:22 2010 -0400
+++ b/src/arch/power/isa/formats/util.isa Sat Mar 27 02:23:00 2010 -0400
@@ -97,9 +97,6 @@
mem_flags = makeList(mem_flags)
inst_flags = makeList(inst_flags)
- # add hook to get effective addresses into execution trace output.
- ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
-
# Generate InstObjParams for the memory access.
iop = InstObjParams(name, Name, base_class,
{'ea_code': ea_code,
diff -r d4921c2e136b -r 6531ddc70176 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Sat Mar 27 02:21:22 2010 -0400
+++ b/src/cpu/inorder/resources/cache_unit.cc Sat Mar 27 02:23:00 2010 -0400
@@ -443,6 +443,10 @@
//The size of the data we're trying to read.
int dataSize = sizeof(T);
+ if (inst->traceData) {
+ inst->traceData->setAddr(addr);
+ }
+
if (inst->split2ndAccess) {
dataSize = inst->split2ndSize;
cache_req->splitAccess = true;
@@ -541,6 +545,11 @@
//The size of the data we're trying to read.
int dataSize = sizeof(T);
+ if (inst->traceData) {
+ inst->traceData->setAddr(addr);
+ inst->traceData->setData(data);
+ }
+
if (inst->split2ndAccess) {
dataSize = inst->split2ndSize;
cache_req->splitAccess = true;
diff -r d4921c2e136b -r 6531ddc70176 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Sat Mar 27 02:21:22 2010 -0400
+++ b/src/cpu/simple/atomic.cc Sat Mar 27 02:23:00 2010 -0400
@@ -351,10 +351,6 @@
}
}
- // This will need a new way to tell if it has a dcache attached.
- if (req->isUncacheable())
- recordEvent("Uncached Read");
-
//If there's a fault, return it
if (fault != NoFault) {
if (req->isPrefetch()) {
@@ -451,6 +447,7 @@
if (traceData) {
traceData->setAddr(addr);
+ traceData->setData(data);
}
//The block size of our peer.
@@ -522,20 +519,10 @@
}
}
- // This will need a new way to tell if it's hooked up to a cache or
not.
- if (req->isUncacheable())
- recordEvent("Uncached Write");
-
//If there's a fault or we don't need to access a second cache line,
//stop now.
if (fault != NoFault || secondAddr <= addr)
{
- // If the write needs to have a fault on the access, consider
- // calling changeStatus() and changing it to "bad addr write"
- // or something.
- if (traceData) {
- traceData->setData(gtoh(data));
- }
if (req->isLocked() && fault == NoFault) {
assert(locked);
locked = false;
diff -r d4921c2e136b -r 6531ddc70176 src/cpu/simple/base.cc
--- a/src/cpu/simple/base.cc Sat Mar 27 02:21:22 2010 -0400
+++ b/src/cpu/simple/base.cc Sat Mar 27 02:23:00 2010 -0400
@@ -205,6 +205,27 @@
{
}
+void
+BaseSimpleCPU::prefetch(Addr addr, unsigned flags)
+{
+ if (traceData) {
+ traceData->setAddr(addr);
+ }
+
+ // need to do this...
+}
+
+void
+BaseSimpleCPU::writeHint(Addr addr, int size, unsigned flags)
+{
+ if (traceData) {
+ traceData->setAddr(addr);
+ }
+
+ // need to do this...
+}
+
+
Fault
BaseSimpleCPU::copySrcTranslate(Addr src)
{
diff -r d4921c2e136b -r 6531ddc70176 src/cpu/simple/base.hh
--- a/src/cpu/simple/base.hh Sat Mar 27 02:21:22 2010 -0400
+++ b/src/cpu/simple/base.hh Sat Mar 27 02:23:00 2010 -0400
@@ -232,16 +232,8 @@
Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
M5_DUMMY_RETURN}
- void prefetch(Addr addr, unsigned flags)
- {
- // need to do this...
- }
-
- void writeHint(Addr addr, int size, unsigned flags)
- {
- // need to do this...
- }
-
+ void prefetch(Addr addr, unsigned flags);
+ void writeHint(Addr addr, int size, unsigned flags);
Fault copySrcTranslate(Addr src);
diff -r d4921c2e136b -r 6531ddc70176 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Sat Mar 27 02:21:22 2010 -0400
+++ b/src/cpu/simple/timing.cc Sat Mar 27 02:23:00 2010 -0400
@@ -426,16 +426,16 @@
int data_size = sizeof(T);
BaseTLB::Mode mode = BaseTLB::Read;
+ if (traceData) {
+ traceData->setAddr(addr);
+ }
+
RequestPtr req = new Request(asid, addr, data_size,
flags, pc, _cpuId, tid);
Addr split_addr = roundDown(addr + data_size - 1, block_size);
assert(split_addr <= addr || split_addr - addr < block_size);
- // This will need a new way to tell if it's hooked up to a cache or not.
- if (req->isUncacheable())
- recordEvent("Uncached Write");
-
_status = DTBWaitResponse;
if (split_addr > addr) {
RequestPtr req1, req2;
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