changeset d4921c2e136b in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=d4921c2e136b description: inorder: update twolf/vortex regressions
diffstat: 4 files changed, 15 insertions(+), 17 deletions(-) tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout | 6 +++--- tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt | 8 ++++---- tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout | 8 +++----- tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 10 +++++----- diffs (87 lines): diff -r 4524f8f80973 -r d4921c2e136b tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout Sat Mar 27 01:40:05 2010 -0400 +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout Sat Mar 27 02:21:22 2010 -0400 @@ -5,9 +5,9 @@ All Rights Reserved -M5 compiled Mar 22 2010 20:37:53 -M5 revision 8f0f6a2f2f48 7039 default qtip tip inorder_twolf qbase -M5 started Mar 22 2010 20:37:54 +M5 compiled Mar 27 2010 01:50:13 +M5 revision e00bda288de7 7046 default qtip tip update_regrs +M5 started Mar 27 2010 01:50:14 M5 executing on zooks command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second diff -r 4524f8f80973 -r d4921c2e136b tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt Sat Mar 27 01:40:05 2010 -0400 +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt Sat Mar 27 02:21:22 2010 -0400 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 52039 # Simulator instruction rate (inst/s) +host_inst_rate 49066 # Simulator instruction rate (inst/s) host_mem_usage 166880 # Number of bytes of host memory used -host_seconds 1697.59 # Real time elapsed on the host -host_tick_rate 62436709 # Simulator tick rate (ticks/s) +host_seconds 1800.43 # Real time elapsed on the host +host_tick_rate 58870361 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.105992 # Number of seconds simulated @@ -30,7 +30,7 @@ system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 82202 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 41101 # Number of Multiply Requests Processed. -system.cpu.RegFile-Manager.instReqsProcessed 165784566 # Number of Instructions Requests that completed in this resource. +system.cpu.RegFile-Manager.instReqsProcessed 165553324 # Number of Instructions Requests that completed in this resource. system.cpu.activity 85.622201 # Percentage of cycles cpu is active system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total) diff -r 4524f8f80973 -r d4921c2e136b tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout Sat Mar 27 01:40:05 2010 -0400 +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout Sat Mar 27 02:21:22 2010 -0400 @@ -5,13 +5,11 @@ All Rights Reserved -M5 compiled Mar 22 2010 23:40:09 -M5 revision ec3385b5d6df 7040 default qtip tip inorder_twolf_update -M5 started Mar 22 2010 23:40:10 +M5 compiled Mar 27 2010 01:41:24 +M5 revision e00bda288de7 7046 default qtip tip update_regrs +M5 started Mar 27 2010 01:46:24 M5 executing on zooks command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff -r 4524f8f80973 -r d4921c2e136b tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt Sat Mar 27 01:40:05 2010 -0400 +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt Sat Mar 27 02:21:22 2010 -0400 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 53958 # Simulator instruction rate (inst/s) -host_mem_usage 156280 # Number of bytes of host memory used -host_seconds 1703.24 # Real time elapsed on the host -host_tick_rate 57999569 # Simulator tick rate (ticks/s) +host_inst_rate 50762 # Simulator instruction rate (inst/s) +host_mem_usage 156288 # Number of bytes of host memory used +host_seconds 1810.49 # Real time elapsed on the host +host_tick_rate 54563823 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.098787 # Number of seconds simulated @@ -30,7 +30,7 @@ system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 916504 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 458252 # Number of Multiply Requests Processed. -system.cpu.RegFile-Manager.instReqsProcessed 196152147 # Number of Instructions Requests that completed in this resource. +system.cpu.RegFile-Manager.instReqsProcessed 196150555 # Number of Instructions Requests that completed in this resource. system.cpu.activity 96.136450 # Percentage of cycles cpu is active system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
