Hello, guys: For studying EDGE ( Explicit Data Graph Execution ) architecture, I spent some time to make M5 simulator to support it.
I have done two things: 1). Adding a CPU model, which is based on O3-CPU model of M5, to support explicitly data-flow execution. This model includes an inst-block predictor, an IQ with explicit data-flow execution supporting, an LSQ, an inst-block RoB, etc. 2). Describing TRIPS ISA ( an instance of EDGE ) using M5 ISA description language. I have made some trivial changes in isa_parser.py to support describing TRIPS ISA which is rather different with conventional RISC/CISC ISA. This model is able to execute binaries generated by TRIPS tool-chain. All the CPU2000 benchmarks supported by TRIPS tool-chain have ran successfully in a reasonable speed. I'm willing to contribute to the M5 community however, I have no idea how to share my codes with you guys. If my achievement is worth to share, could anybody give me some guides of sharing my codes. If my achievement is not so interesting, could anybody give me some suggestions of how to improve it. Thank you all. Best wishes to all of you guys. -- Gou Pengfei Ph.D. candidate Harbin Institute of Technology, China
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