Hi Ali: Sorry for delaying sharing my code. I have some issues to deal with recent days. I am planning to share my code due to May. 3.
Sorry again. pengfei 在 2010年4月28日 上午7:40，Ali Saidi <[email protected]>写道： > Hi Pengfei, > > I don't want to loose your patches, so I just wanted to follow up and check > that you still intended to share them. > > Thanks, > > Ali > > On Apr 14, 2010, at 11:15 AM, Pengfei Gou wrote: > > > Hi Ali: > > > > Sorry for not checking the Adding Functionality pages in M5 wiki, which > is really helpful for me to share my codes with you guys. > > > > Since I use SVN as my source control scheme, I need a few days to get > familiar with HG so that I can push my patches into m5-dev list for you to > evaluate them. > > > > Thanks for your kind reply. > > > > I will be back in a couple of days. > > > > 2010/4/14 Ali Saidi <[email protected]> > > > > Hi Pengfei, > > > > We would definitely welcome your contribution. Normally patches are sent > to > > the m5-dev list. While this is pretty reasonable for a few patches to a > > handful of files, it's more complex with all the files I imagine you'll > be > > changing/patching/etc. Please give us a few days to see if we can come up > > with a better method to evaluate your code for inclusion in M5. At that > > time we'll be very interested to see your work and thank you for taking > the > > time to contribute it back to the M5 community. > > > > Ali > > > > On Tue, 13 Apr 2010 21:51:33 +0800, Pengfei Gou <[email protected]> > > wrote: > > > Hello, guys: > > > > > > For studying EDGE ( Explicit Data Graph Execution ) architecture, I > spent > > > some time to make M5 simulator to support it. > > > > > > I have done two things: > > > 1). Adding a CPU model, which is based on O3-CPU model of M5, to > support > > > explicitly data-flow execution. This model includes an inst-block > > > predictor, > > > an IQ with explicit data-flow execution supporting, an LSQ, an > inst-block > > > RoB, etc. > > > > > > 2). Describing TRIPS ISA ( an instance of EDGE ) using M5 ISA > description > > > language. I have made some trivial changes in isa_parser.py to support > > > describing TRIPS ISA which is rather different with conventional > > RISC/CISC > > > ISA. > > > > > > This model is able to execute binaries generated by TRIPS tool-chain. > All > > > the CPU2000 benchmarks supported by TRIPS tool-chain have ran > > successfully > > > in a reasonable speed. > > > > > > I'm willing to contribute to the M5 community however, I have no idea > how > > > to > > > share my codes with you guys. > > > > > > If my achievement is worth to share, could anybody give me some guides > of > > > sharing my codes. If my achievement is not so interesting, could > anybody > > > give me some suggestions of how to improve it. > > > > > > Thank you all. > > > > > > Best wishes to all of you guys. > > _______________________________________________ > > m5-dev mailing list > > [email protected] > > http://m5sim.org/mailman/listinfo/m5-dev > > > > > > > > -- > > 苟鹏飞 > > 哈尔滨工业大学 > > 微电子中心 > > _______________________________________________ > > m5-dev mailing list > > [email protected] > > http://m5sim.org/mailman/listinfo/m5-dev > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > -- 苟鹏飞 哈尔滨工业大学 微电子中心
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