# HG changeset patch
# User Maximilien Breughe <[email protected]>
# Date 1271144311 -7200
# Branch dev-perflab
# Node ID 7ca74951f5b7a4c9b764f3ec61f26d5a3661677a
# Parent 401bc1d45798b11db33cf5c995c7c44fceacc4c3
White-space fix
diff -r 401bc1d45798 -r 7ca74951f5b7
src/cpu/inorder/resources/branch_predictor.cc
--- a/src/cpu/inorder/resources/branch_predictor.cc Tue Apr 13 09:38:04
2010 +0200
+++ b/src/cpu/inorder/resources/branch_predictor.cc Tue Apr 13 09:38:31
2010 +0200
@@ -143,12 +143,12 @@
{
DPRINTF(InOrderBPred, "Squashing...\n");
if(squash_stage>=ThePipeline::BackEndStartStage){
- Addr corr_targ=inst->readPredPC();
- bool taken=inst->predTaken();
- branchPred.squash(squash_seq_num,corr_targ,taken,tid);
+ Addr corr_targ=inst->readPredPC();
+ bool taken=inst->predTaken();
+ branchPred.squash(squash_seq_num,corr_targ,taken,tid);
}
- else
- branchPred.squash(squash_seq_num,tid);
+ else
+ branchPred.squash(squash_seq_num,tid);
}
void
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