# HG changeset patch
# User Maximilien Breughe <[email protected]>
# Date 1271235260 -7200
# Branch dev-perflab
# Node ID 55ae031000c1798a4919d5f807e3a58432806b36
# Parent 7ca74951f5b7a4c9b764f3ec61f26d5a3661677a
Fixed some style issues
diff -r 7ca74951f5b7 -r 55ae031000c1
src/cpu/inorder/resources/branch_predictor.cc
--- a/src/cpu/inorder/resources/branch_predictor.cc Tue Apr 13 09:38:31
2010 +0200
+++ b/src/cpu/inorder/resources/branch_predictor.cc Wed Apr 14 10:54:20
2010 +0200
@@ -142,13 +142,13 @@
InstSeqNum squash_seq_num, ThreadID tid)
{
DPRINTF(InOrderBPred, "Squashing...\n");
- if(squash_stage>=ThePipeline::BackEndStartStage){
- Addr corr_targ=inst->readPredPC();
- bool taken=inst->predTaken();
- branchPred.squash(squash_seq_num,corr_targ,taken,tid);
+ if (squash_stage >= ThePipeline::BackEndStartStage) {
+ Addr corr_targ = inst->readPredPC();
+ bool taken = inst->predTaken();
+ branchPred.squash(squash_seq_num, corr_targ, taken, tid);
+ } else {
+ branchPred.squash(squash_seq_num, tid);
}
- else
- branchPred.squash(squash_seq_num,tid);
}
void
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
