changeset d915b0f60b22 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d915b0f60b22
description:
BPRED: Update regressions for tournament predictor fix.
diffstat:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini |
2 +-
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout |
8 +-
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt |
664 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini |
2 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout |
10 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt |
636 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini |
12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr |
2 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout |
12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt |
1960 ++++----
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini |
12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout |
12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt |
956 ++--
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini |
4 +-
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout |
10 +-
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt |
632 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini |
2 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout |
8 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt |
638 +-
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout |
8 +-
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt |
268 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini |
2 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout |
8 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt |
662 +-
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout |
10 +-
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt |
262 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini |
2 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout |
10 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt |
648 +-
tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout |
10 +-
tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt |
198 +-
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini |
2 +-
tests/quick/00.hello/ref/alpha/linux/o3-timing/simout |
12 +-
tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt |
526 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini |
2 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout |
10 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt |
487 +-
tests/quick/00.hello/ref/mips/linux/inorder-timing/simout |
8 +-
tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt |
8 +-
tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini |
2 +-
tests/quick/00.hello/ref/mips/linux/o3-timing/simout |
10 +-
tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt |
384 +-
tests/quick/00.hello/ref/power/linux/o3-timing/config.ini |
2 +-
tests/quick/00.hello/ref/power/linux/o3-timing/simerr |
2 +-
tests/quick/00.hello/ref/power/linux/o3-timing/simout |
10 +-
tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt |
518 +-
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini |
4 +-
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout |
10 +-
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt |
841 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini |
2 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout |
10 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt |
464 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini |
2 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout |
72 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt |
2270 +++++-----
55 files changed, 6666 insertions(+), 6662 deletions(-)
diffs (truncated from 17212 to 300 lines):
diff -r 070529b41c1e -r d915b0f60b22
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Thu May 13
23:45:57 2010 -0400
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Thu May 13
23:45:59 2010 -0400
@@ -358,7 +358,7 @@
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
diff -r 070529b41c1e -r d915b0f60b22
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Thu May 13
23:45:57 2010 -0400
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Thu May 13
23:45:59 2010 -0400
@@ -5,10 +5,10 @@
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:02:05
-M5 executing on SC2B0619
+M5 compiled May 12 2010 01:43:39
+M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip
+M5 started May 12 2010 01:52:49
+M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff -r 070529b41c1e -r d915b0f60b22
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Thu May 13
23:45:57 2010 -0400
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Thu May 13
23:45:59 2010 -0400
@@ -1,340 +1,340 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 207071 #
Simulator instruction rate (inst/s)
-host_mem_usage 192708 #
Number of bytes of host memory used
-host_seconds 2731.20 #
Real time elapsed on the host
-host_tick_rate 61173967 #
Simulator tick rate (ticks/s)
+host_inst_rate 206060 #
Simulator instruction rate (inst/s)
+host_mem_usage 206972 #
Number of bytes of host memory used
+host_seconds 2744.60 #
Real time elapsed on the host
+host_tick_rate 61062862 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 565552443 #
Number of instructions simulated
-sim_seconds 0.167078 #
Number of seconds simulated
-sim_ticks 167078146500 #
Number of ticks simulated
+sim_seconds 0.167593 #
Number of seconds simulated
+sim_ticks 167593085500 #
Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 65718859 #
Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 73181368 #
Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 198 #
Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 4206850 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 70112287 #
Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 76039018 #
Number of BP lookups
-system.cpu.BPredUnit.usedRAS 1692219 #
Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits 63922842 #
Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 71487962 #
Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 180 #
Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 4121924 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 70504427 #
Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 76440051 #
Number of BP lookups
+system.cpu.BPredUnit.usedRAS 1674270 #
Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 62547159 #
Number of branches committed
-system.cpu.commit.COM:bw_lim_events 17700250 #
number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 18448626 #
number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 #
number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 322711250
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.865001
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 2.301723
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 323575021
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.860023
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 2.297815
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00%
0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0-1 108088758 33.49%
33.49% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1-2 100475751 31.13%
64.63% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2-3 37367184 11.58%
76.21% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3-4 9733028 3.02%
79.22% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4-5 10676883 3.31%
82.53% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5-6 22147835 6.86%
89.40% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6-7 13251874 4.11%
93.50% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7-8 3269687 1.01%
94.52% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 17700250 5.48%
100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0-1 107931872 33.36%
33.36% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1-2 101513205 31.37%
64.73% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2-3 37265964 11.52%
76.25% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3-4 10166735 3.14%
79.39% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4-5 11290718 3.49%
82.88% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5-6 21721468 6.71%
89.59% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6-7 12702626 3.93%
93.52% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7-8 2533807 0.78%
94.30% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 18448626 5.70%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 322711250
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 323575021
# Number of insts commited each cycle
system.cpu.commit.COM:count 601856963 #
Number of instructions committed
system.cpu.commit.COM:loads 115049510 #
Number of loads committed
system.cpu.commit.COM:membars 0 #
Number of memory barriers committed
system.cpu.commit.COM:refs 154862033 #
Number of memory references committed
system.cpu.commit.COM:swp_count 0 #
Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 4206223 #
The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 4121096 #
The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 601856963 #
The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 61418165 #
The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 61591802 #
The number of squashed insts skipped by commit
system.cpu.committedInsts 565552443 #
Number of Instructions Simulated
system.cpu.committedInsts_total 565552443 #
Number of Instructions Simulated
-system.cpu.cpi 0.590849 #
CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.590849 #
CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 1 #
number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 1 #
number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 113146786 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 19647.173839
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.243845
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 112293703 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 16760670000 #
number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.007540 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 853083 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 636806 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1688311000
# number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 #
mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 216277 #
number of ReadReq MSHR misses
+system.cpu.cpi 0.592670 #
CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.592670 #
CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 4 #
number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits 4 #
number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses 113443216 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 19248.740390
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7746.370369
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 112634831 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 15560393000 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.007126 #
miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 808385 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 590181 #
number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1690289000
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001923 #
mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 218204 #
number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 39451321 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 32801.298408
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35637.649046
# average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 37121636 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 76416692881 #
number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.059052 #
miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2329685 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1992407 #
number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995
# number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 #
mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 337278 #
number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 6922.723577
# average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 21318.181818
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 317.179202 #
Average number of references to valid blocks.
+system.cpu.dcache.WriteReq_avg_miss_latency 32797.392555
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35638.802347
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 37116231 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 76584863381 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.059189 #
miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 2335090 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1996724 #
number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 12058958995
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.008577 #
mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 338366 #
number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 6528.414634
# average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 21363.636364
# average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 316.462124 #
Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 123 #
number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 #
number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 851495
# number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 234500
# number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 802995
# number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 235000
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses 152598107 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 29275.574871 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 24763.765109
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 149415339 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 93177362881 #
number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.020857 #
miss rate for demand accesses
-system.cpu.dcache.demand_misses 3182768 #
number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2629213 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 13708105995
# number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003628 #
mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 553555 #
number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 152894537 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 29313.182507 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 24703.537731
# average overall mshr miss latency
+system.cpu.dcache.demand_hits 149751062 #
number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 92145256381 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.020560 #
miss rate for demand accesses
+system.cpu.dcache.demand_misses 3143475 #
number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2586905 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 13749247995
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.003640 #
mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 556570 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999561 #
Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4094.203417 #
Average occupied blocks per context
-system.cpu.dcache.overall_accesses 152598107 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 29275.574871
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109
# average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.999563 #
Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4094.208277 #
Average occupied blocks per context
+system.cpu.dcache.overall_accesses 152894537 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 29313.182507
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 24703.537731
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 149415339 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 93177362881 #
number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.020857 #
miss rate for overall accesses
-system.cpu.dcache.overall_misses 3182768 #
number of overall misses
-system.cpu.dcache.overall_mshr_hits 2629213 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 13708105995
# number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003628 #
mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 553555 #
number of overall MSHR misses
+system.cpu.dcache.overall_hits 149751062 #
number of overall hits
+system.cpu.dcache.overall_miss_latency 92145256381 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.020560 #
miss rate for overall accesses
+system.cpu.dcache.overall_misses 3143475 #
number of overall misses
+system.cpu.dcache.overall_mshr_hits 2586905 #
number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 13749247995
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.003640 #
mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 556570 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 468828 #
number of replacements
-system.cpu.dcache.sampled_refs 472924 #
Sample count of references to valid blocks.
+system.cpu.dcache.replacements 470982 #
number of replacements
+system.cpu.dcache.sampled_refs 475078 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.203417 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 150001657 #
Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 126581000 #
Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 334123 #
number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 49202518 #
Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 654 #
Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 4158991 #
Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 689696194 #
Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 144199483 #
Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 123896058 #
Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 9869862 #
Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 2004 #
Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 5413191 #
Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 163077390 #
DTB accesses
+system.cpu.dcache.tagsinuse 4094.208277 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 150344193 #
Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 126612000 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 335213 #
number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 51119249 #
Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 861 #
Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 4177292 #
Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 689843810 #
Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 144051375 #
Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 122990983 #
Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 9853353 #
Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 3386 #
Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 5413414 #
Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 163070578 #
DTB accesses
system.cpu.dtb.data_acv 0 #
DTB access violations
-system.cpu.dtb.data_hits 163013880 #
DTB hits
-system.cpu.dtb.data_misses 63510 #
DTB misses
+system.cpu.dtb.data_hits 163012019 #
DTB hits
+system.cpu.dtb.data_misses 58559 #
DTB misses
system.cpu.dtb.fetch_accesses 0 #
ITB accesses
system.cpu.dtb.fetch_acv 0 #
ITB acv
system.cpu.dtb.fetch_hits 0 #
ITB hits
system.cpu.dtb.fetch_misses 0 #
ITB misses
-system.cpu.dtb.read_accesses 122284109 #
DTB read accesses
+system.cpu.dtb.read_accesses 122259759 #
DTB read accesses
system.cpu.dtb.read_acv 0 #
DTB read access violations
-system.cpu.dtb.read_hits 122260496 #
DTB read hits
-system.cpu.dtb.read_misses 23613 #
DTB read misses
-system.cpu.dtb.write_accesses 40793281 #
DTB write accesses
+system.cpu.dtb.read_hits 122237048 #
DTB read hits
+system.cpu.dtb.read_misses 22711 #
DTB read misses
+system.cpu.dtb.write_accesses 40810819 #
DTB write accesses
system.cpu.dtb.write_acv 0 #
DTB write access violations
-system.cpu.dtb.write_hits 40753384 #
DTB write hits
-system.cpu.dtb.write_misses 39897 #
DTB write misses
-system.cpu.fetch.Branches 76039018 #
Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 66014406 #
Number of cache lines fetched
-system.cpu.fetch.Cycles 197129335 #
Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 1352914 #
Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 698864013 #
Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 4233115 #
Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.227555 #
Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 66014406 #
Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 67411078 #
Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.091429 #
Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 332581112 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.101334 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.065263 #
Number of instructions fetched each cycle (Total)
+system.cpu.dtb.write_hits 40774971 #
DTB write hits
+system.cpu.dtb.write_misses 35848 #
DTB write misses
+system.cpu.fetch.Branches 76440051 #
Number of branches that fetch encountered
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