changeset 87782b4966d9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=87782b4966d9
description:
BPRED: Update one missing regression
diffstat:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini | 2 +-
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout | 8 +-
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 670 +++++++-------
3 files changed, 340 insertions(+), 340 deletions(-)
diffs (truncated from 822 to 300 lines):
diff -r e4c5fbbc8633 -r 87782b4966d9
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini Fri May 14
14:22:51 2010 -0700
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini Wed May 19
00:36:05 2010 -0400
@@ -358,7 +358,7 @@
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
diff -r e4c5fbbc8633 -r 87782b4966d9
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout Fri May 14
14:22:51 2010 -0700
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout Wed May 19
00:36:05 2010 -0400
@@ -5,10 +5,10 @@
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 02:37:14
-M5 executing on SC2B0619
+M5 compiled May 16 2010 18:46:51
+M5 revision 38e5c8a73ea9 7084 default tip
+M5 started May 16 2010 18:46:55
+M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py
build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff -r e4c5fbbc8633 -r 87782b4966d9
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
--- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt Fri May 14
14:22:51 2010 -0700
+++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt Wed May 19
00:36:05 2010 -0400
@@ -1,54 +1,54 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 176404 #
Simulator instruction rate (inst/s)
-host_mem_usage 192532 #
Number of bytes of host memory used
-host_seconds 9841.32 #
Real time elapsed on the host
-host_tick_rate 75427820 #
Simulator tick rate (ticks/s)
+host_inst_rate 144441 #
Simulator instruction rate (inst/s)
+host_mem_usage 206960 #
Number of bytes of host memory used
+host_seconds 12019.07 #
Real time elapsed on the host
+host_tick_rate 61604184 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 1736043781 #
Number of instructions simulated
-sim_seconds 0.742309 #
Number of seconds simulated
-sim_ticks 742309425500 #
Number of ticks simulated
+sim_seconds 0.740425 #
Number of seconds simulated
+sim_ticks 740424887500 #
Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 312845737 #
Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 319575559 #
Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 136 #
Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 19647325 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 266741494 #
Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 345502589 #
Number of BP lookups
-system.cpu.BPredUnit.usedRAS 23750300 #
Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits 300304269 #
Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 307023866 #
Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 161 #
Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 19915568 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 268271856 #
Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 347819261 #
Number of BP lookups
+system.cpu.BPredUnit.usedRAS 23893430 #
Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 214632552 #
Number of branches committed
-system.cpu.commit.COM:bw_lim_events 62782585 #
number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 63188477 #
number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 #
number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 1379215339
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.319431
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 2.090314
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 1374695730
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.323769
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 2.099460
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00%
0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0-1 736540831 53.40%
53.40% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1-2 260049504 18.85%
72.26% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2-3 126970462 9.21%
81.46% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3-4 77723426 5.64%
87.10% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4-5 51327439 3.72%
90.82% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5-6 27759546 2.01%
92.83% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6-7 26179568 1.90%
94.73% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7-8 9881978 0.72%
95.45% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 62782585 4.55%
100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0-1 733755921 53.38%
53.38% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1-2 260590847 18.96%
72.33% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2-3 127148586 9.25%
81.58% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3-4 73808717 5.37%
86.95% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4-5 48837558 3.55%
90.50% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5-6 32392808 2.36%
92.86% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6-7 24165844 1.76%
94.62% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7-8 10806972 0.79%
95.40% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 63188477 4.60%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 1379215339
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 1374695730
# Number of insts commited each cycle
system.cpu.commit.COM:count 1819780126 #
Number of instructions committed
system.cpu.commit.COM:loads 445666361 #
Number of loads committed
system.cpu.commit.COM:membars 0 #
Number of memory barriers committed
system.cpu.commit.COM:refs 606571343 #
Number of memory references committed
system.cpu.commit.COM:swp_count 0 #
Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 19646824 #
The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 19915049 #
The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1819780126 #
The number of committed instructions
system.cpu.commit.commitNonSpecStalls 29 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 627314235 #
The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 631770816 #
The number of squashed insts skipped by commit
system.cpu.committedInsts 1736043781 #
Number of Instructions Simulated
system.cpu.committedInsts_total 1736043781 #
Number of Instructions Simulated
-system.cpu.cpi 0.855174 #
CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.855174 #
CPI: Total CPI of All Threads
+system.cpu.cpi 0.853003 #
CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.853003 #
CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 3 #
number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500
# average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500
# average LoadLockedReq mshr miss latency
@@ -59,291 +59,291 @@
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500
# number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333
# mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 1
# number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses 523259964 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 16887.792500
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11267.111116
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 512954316 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 174039645000 #
number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.019695 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 10305648 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 3030509 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 81969799500
# number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.013903 #
mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 7275139 #
number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_accesses 523747084 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 16905.655994
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11269.981612
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 513424902 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 174503258000 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.019708 #
miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 10322182 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 3045892 #
number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 82003654500
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.013893 #
mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7276290 #
number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 33917.187245
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.824123
# average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 155297498 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 184204379594 #
number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.033790 #
miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 5431004 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 3182477 #
number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 83541376693
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 33742.228480
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.275529
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 155297365 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 183258665559 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.033791 #
miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 5431137 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 3182597 #
number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 83540626157
# number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 #
mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 2248527 #
number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 6337.465393
# average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 31613.485382
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 73.053349 #
Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 156253 #
number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 65330 #
number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 990247980
# number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 2065309000
# number of cycles access was blocked
+system.cpu.dcache.WriteReq_mshr_misses 2248540 #
number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 6330.872599
# average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 30366.853399
# average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 73.096818 #
Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 156412 #
number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 65334 #
number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 990224445
# number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 1983988000
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses 683988466 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 22764.945466 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 17378.935401
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 668251814 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 358244024594 #
number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.023007 #
miss rate for demand accesses
-system.cpu.dcache.demand_misses 15736652 #
number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 6212986 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 165511176193
# number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.013924 #
mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9523666 #
number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 684475586 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 22710.257030 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 17380.287171
# average overall mshr miss latency
+system.cpu.dcache.demand_hits 668722267 #
number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 357761923559 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.023015 #
miss rate for demand accesses
+system.cpu.dcache.demand_misses 15753319 #
number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 6228489 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 165544280657
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.013916 #
mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9524830 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.997499 #
Average percentage of cache occupancy
-system.cpu.dcache.occ_%::1 -0.003145 #
Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4085.757368 #
Average occupied blocks per context
-system.cpu.dcache.occ_blocks::1 -12.883149 #
Average occupied blocks per context
-system.cpu.dcache.overall_accesses 683988466 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 22764.945466
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 17378.935401
# average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.997494 #
Average percentage of cache occupancy
+system.cpu.dcache.occ_%::1 -0.003143 #
Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4085.737319 #
Average occupied blocks per context
+system.cpu.dcache.occ_blocks::1 -12.874688 #
Average occupied blocks per context
+system.cpu.dcache.overall_accesses 684475586 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 22710.257030
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 17380.287171
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 668251814 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 358244024594 #
number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.023007 #
miss rate for overall accesses
-system.cpu.dcache.overall_misses 15736652 #
number of overall misses
-system.cpu.dcache.overall_mshr_hits 6212986 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 165511176193
# number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.013924 #
mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9523666 #
number of overall MSHR misses
+system.cpu.dcache.overall_hits 668722267 #
number of overall hits
+system.cpu.dcache.overall_miss_latency 357761923559 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.023015 #
miss rate for overall accesses
+system.cpu.dcache.overall_misses 15753319 #
number of overall misses
+system.cpu.dcache.overall_mshr_hits 6228489 #
number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 165544280657
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.013916 #
mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9524830 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 9155775 #
number of replacements
-system.cpu.dcache.sampled_refs 9159871 #
Sample count of references to valid blocks.
+system.cpu.dcache.replacements 9156903 #
number of replacements
+system.cpu.dcache.sampled_refs 9160999 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4079.315794 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 669159251 #
Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 7089291000 #
Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2245449 #
number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 98604488 #
Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 553 #
Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 54363606 #
Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 2810650778 #
Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 726334611 #
Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 549143104 #
Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 93084202 #
Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 1641 #
Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 5133136 #
Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 768331641 #
DTB accesses
+system.cpu.dcache.tagsinuse 4079.299976 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 669639874 #
Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 7084220000 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2245460 #
number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 97965081 #
Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 741 #
Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 54990106 #
Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 2817972216 #
Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 726420898 #
Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 545630418 #
Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 93906879 #
Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 1735 #
Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 4679333 #
Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 771953785 #
DTB accesses
system.cpu.dtb.data_acv 0 #
DTB access violations
-system.cpu.dtb.data_hits 752318840 #
DTB hits
-system.cpu.dtb.data_misses 16012801 #
DTB misses
+system.cpu.dtb.data_hits 755880744 #
DTB hits
+system.cpu.dtb.data_misses 16073041 #
DTB misses
system.cpu.dtb.fetch_accesses 0 #
ITB accesses
system.cpu.dtb.fetch_acv 0 #
ITB acv
system.cpu.dtb.fetch_hits 0 #
ITB hits
system.cpu.dtb.fetch_misses 0 #
ITB misses
-system.cpu.dtb.read_accesses 566617553 #
DTB read accesses
+system.cpu.dtb.read_accesses 569575118 #
DTB read accesses
system.cpu.dtb.read_acv 0 #
DTB read access violations
-system.cpu.dtb.read_hits 557381527 #
DTB read hits
-system.cpu.dtb.read_misses 9236026 #
DTB read misses
-system.cpu.dtb.write_accesses 201714088 #
DTB write accesses
+system.cpu.dtb.read_hits 560292416 #
DTB read hits
+system.cpu.dtb.read_misses 9282702 #
DTB read misses
+system.cpu.dtb.write_accesses 202378667 #
DTB write accesses
system.cpu.dtb.write_acv 0 #
DTB write access violations
-system.cpu.dtb.write_hits 194937313 #
DTB write hits
-system.cpu.dtb.write_misses 6776775 #
DTB write misses
-system.cpu.fetch.Branches 345502589 #
Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 355180518 #
Number of cache lines fetched
-system.cpu.fetch.Cycles 920206770 #
Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 7941781 #
Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 2863046502 #
Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 28103165 #
Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.232721 #
Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 355180518 #
Number of cycles fetch is stalled on an Icache miss
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