Hi,
We are trying to connect a dummy cpu model to caches. So we require to
connect the icache and dcache ports of this dummy cpu model to that of M5
caches. Can anybody please tell us what is the best way to achieve this
connection ?Arka & Rathijit _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
