On Sun, Jun 13, 2010 at 12:04 PM, Gabe Black <[email protected]> wrote: > Gabe Black wrote: > > I just thought of another, more important drawback. In an in order > pipeline, the writeback will take up an extra pipeline stage, > effectively adding a bubble. In reality, I'd imagine the update would be > computed in the execute stage at the same time as the address > computation. This is especially important for ARM which, if I'm not > mistaken, is usually implemented as an in order pipeline.
The thing to keep in mind is that a load with update actually updates two registers (the load target and the effective address reg) and thus typically does require two writeback cycles, potentially introducing a bubble (since it's overkill to add a second reg write port just for this instruction). So as is not so infrequently the case, simulation awkwardness reflects real-world implementation awkwardness. To be honest I don't think it's unreasonable to code stores with updates as a single instruction but to microcode the loads with updates. You'd have to ask someone who works for ARM to what extent this is reflects the reality of modern ARM core designs. Steve _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
