It could use some cleanup. The idea has always been that it's the simplest CPU that can drive the timing memory system, so there's no guarantee it will be simple in an absolute sense. But I'm sure it could be simpler if we worked at it. I think the combination of dealing with unaligned accesses and split-phase translations has definitely hit it hard.
Steve On Sat, Jun 5, 2010 at 1:45 PM, Ali Saidi <[email protected]> wrote: > My comment was more that we might want to re-evaluate the timing simple cpu > as it's left the simple bit a while ago. Many of the fault == NoFault checks > don't matter with the translation state change since it's always going to > return no fault. > > > I was hoping to get a discussion going about what if anything we should do. > > Ali > > On Jun 4, 2010, at 5:29 PM, nathan binkert wrote: > >>> On a somewhat related note, it seems like the timing simple cpu control >>> flow has gotten pretty messy with the addition of the translation state >>> code. To figure out what is going on you really need a large white board >>> and a lot of time to map out the call tree and what happens on faults and >>> the like. >> >> Ali, >> >> If it is correct, can you commit the patch? If you're not the right >> person, Gabe? >> >> Nate >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev >> > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
