> > 1. An in-order CPU module with multi-threading (switching threads upon > cache > > accesses) based on TimingSimpleCPU > This is probably #1 on the priority list > Is this inorder model detailed (in terms of pipeline stages, branch prediciton, Functional Units, etc.)?
Is it functional within Full system mode? I'm guessing that this would be a good contribution but I'm wondering if this would somewhat antiquate the actual inorderCPU model that is already in the development tree? -- - Korey
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