> On 2010-07-22 00:26:07, Gabe Black wrote: > > src/cpu/o3/lsq_unit.hh, line 825 > > <http://reviews.m5sim.org/r/54/diff/1/?file=769#file769line825> > > > > Is it possible for sreqLow to be non-null and > > TheISA::HasUnalignedMemAcc -not- to be true? In that instance, wouldn't > > this still be a split access? Or does the code not shown in this diff make > > that not work? > > > > If this is just to make it more obvious what sort of condition your > > checking for a comment would be better, or if it's a sanity check sort of > > thing an assert.
This case should never happen. In BaseDynInst<Impl>::read and BaseDynInst<Impl>::write, sreqLow and sreqHigh get set to NULL. They are only set non-null when a request is split in two, which can only happen if TheISA::HasUnalignedMemAcc is true (and the access crosses a cache line boundary). I'll add a comment into the code to clarify what's happening. - Timothy ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/54/#review105 ----------------------------------------------------------- On 2010-07-09 18:20:19, Timothy Jones wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/54/ > ----------------------------------------------------------- > > (Updated 2010-07-09 18:20:19) > > > Review request for Default. > > > Summary > ------- > > O3CPU: Fix a bug where stores in the cpu where never marked as split. > > > Diffs > ----- > > src/cpu/o3/lsq_unit.hh 249f174e6f37 > > Diff: http://reviews.m5sim.org/r/54/diff > > > Testing > ------- > > > Thanks, > > Timothy > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
