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Review request for Default and Min Kyu Jeong. Summary ------- ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate. THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false. Diffs ----- src/arch/arm/isa/templates/mem.isa 3c48b2b3cb83 src/arch/arm/isa/templates/pred.isa 3c48b2b3cb83 src/cpu/base_dyn_inst.hh 3c48b2b3cb83 src/cpu/base_dyn_inst_impl.hh 3c48b2b3cb83 src/cpu/o3/lsq_unit_impl.hh 3c48b2b3cb83 src/cpu/simple/base.hh 3c48b2b3cb83 src/cpu/simple_thread.hh 3c48b2b3cb83 src/cpu/thread_context.hh 3c48b2b3cb83 Diff: http://reviews.m5sim.org/r/177/diff Testing ------- Thanks, Ali _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
