Anyone have comments on this? It seems like this is the only way to access the DynInst from the isa description. Threadstate does have the current instruction in it, as well as things like "Temporary storage to pass the source address from copy_load to". It doesn't seem to out of place to include current instruction predication state in there.
Ali On Sat, 14 Aug 2010 07:08:35 -0000, "Gabe Black" <[email protected]> wrote: > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/177/#review185 > ----------------------------------------------------------- > > > > src/cpu/thread_context.hh > <http://reviews.m5sim.org/r/177/#comment326> > > This isn't really a property of a thread, it's the property of a > single instruction. I don't think this is being done in the right > place. I think we should have a discussion on m5-dev to determine the > best way to handle this. There was a little code added to the simple > CPU that does what this is supposed to do if a memory instruction > didn't actually read or write memory, and I think this is a better way > to handle this. We should have a discussion about this on m5-dev, > especially since it touches lots of low level bits like *contexts, > instruction behavior, CPUs, etc. These sorts of changes need to be made > carefully. > > > - Gabe > > > On 2010-08-13 10:12:35, Ali Saidi wrote: >> >> ----------------------------------------------------------- >> This is an automatically generated e-mail. To reply, visit: >> http://reviews.m5sim.org/r/177/ >> ----------------------------------------------------------- >> >> (Updated 2010-08-13 10:12:35) >> >> >> Review request for Default and Min Kyu Jeong. >> >> >> Summary >> ------- >> >> ARM/O3: store the result of the predicate evaluation in DynInst or >> Threadstate. >> THis allows the CPU to handle predicated-false instructions accordingly. >> This particular patch makes loads that are predicated-false to be sent >> straight to the commit stage directly, not waiting for return of the data >> that was never requested since it was predicated-false. >> >> >> Diffs >> ----- >> >> src/arch/arm/isa/templates/mem.isa 3c48b2b3cb83 >> src/arch/arm/isa/templates/pred.isa 3c48b2b3cb83 >> src/cpu/base_dyn_inst.hh 3c48b2b3cb83 >> src/cpu/base_dyn_inst_impl.hh 3c48b2b3cb83 >> src/cpu/o3/lsq_unit_impl.hh 3c48b2b3cb83 >> src/cpu/simple/base.hh 3c48b2b3cb83 >> src/cpu/simple_thread.hh 3c48b2b3cb83 >> src/cpu/thread_context.hh 3c48b2b3cb83 >> >> Diff: http://reviews.m5sim.org/r/177/diff >> >> >> Testing >> ------- >> >> >> Thanks, >> >> Ali >> >> > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
