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Review request for Default. Summary ------- MEM: Make CLREX a first class request operation and clear locks in caches when it in received Diffs ----- src/arch/arm/isa/insts/misc.isa 3c48b2b3cb83 src/arch/arm/isa/templates/misc.isa 3c48b2b3cb83 src/arch/arm/tlb.hh 3c48b2b3cb83 src/arch/arm/tlb.cc 3c48b2b3cb83 src/mem/cache/cache_impl.hh 3c48b2b3cb83 src/mem/cache/tags/base.hh 3c48b2b3cb83 src/mem/cache/tags/fa_lru.hh 3c48b2b3cb83 src/mem/cache/tags/fa_lru.cc 3c48b2b3cb83 src/mem/cache/tags/iic.hh 3c48b2b3cb83 src/mem/cache/tags/iic.cc 3c48b2b3cb83 src/mem/cache/tags/lru.hh 3c48b2b3cb83 src/mem/cache/tags/lru.cc 3c48b2b3cb83 src/mem/request.hh 3c48b2b3cb83 Diff: http://reviews.m5sim.org/r/193/diff Testing ------- Thanks, Ali _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
