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src/cpu/o3/lsq_unit_impl.hh <http://reviews.m5sim.org/r/178/#comment327> Why doesn't the normal branch mispredict logic catch this? I'm betting instructions that normally wouldn't be branches but that modify the PC aren't being marked as branches in the decoder, and that may or may not be contributing to this problem. This change may be necessary, but I'm skeptical. - Gabe On 2010-08-13 10:12:44, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/178/ > ----------------------------------------------------------- > > (Updated 2010-08-13 10:12:44) > > > Review request for Default and Min Kyu Jeong. > > > Summary > ------- > > O3: Handle loads when the destination is the PC. > For loads that PC is the destination, check if the load > was mispredicted again when the value being loaded returns from memory > > > Diffs > ----- > > src/cpu/o3/iew.hh 3c48b2b3cb83 > src/cpu/o3/iew_impl.hh 3c48b2b3cb83 > src/cpu/o3/lsq_unit.hh 3c48b2b3cb83 > src/cpu/o3/lsq_unit_impl.hh 3c48b2b3cb83 > > Diff: http://reviews.m5sim.org/r/178/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
