> On 2010-08-14 00:14:09, Gabe Black wrote: > > src/cpu/o3/lsq_unit_impl.hh, line 994 > > <http://reviews.m5sim.org/r/178/diff/1/?file=1877#file1877line994> > > > > Why doesn't the normal branch mispredict logic catch this? > > > > I'm betting instructions that normally wouldn't be branches but that > > modify the PC aren't being marked as branches in the decoder, and that may > > or may not be contributing to this problem. This change may be necessary, > > but I'm skeptical. > > Min Kyu Jeong wrote: > Normally, branch misprediction is checked right after the instruction is > executed because we know the result immediately (or some fixed-cycle latency > but I don't believe that is being modeled). However, load instruction is a > split-transaction and therefore we need to have the check at the finishing > end of the split transaction.
I haven't actually verified what you're saying myself, but it sounds very plausible. Since most instructions in ARM and, apparently, all instructions in other ISAs won't need this code, you might want to only run it if the instruction is marked as a branch. You'd also need to make sure those instructions actually -are- marked as branches, but you'd want to do that anyway to really be correct. It would also be best, if at all possible, for this to go through the same mispredict and branch predictor updating logic as other instructions. That way we don'd duplicate the code, especially code that applies so infrequently and might not be run without really thorough testing, and we make sure the predictor gets involved and we don't mispredict on every load to the PC. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/178/#review186 ----------------------------------------------------------- On 2010-08-13 10:12:44, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/178/ > ----------------------------------------------------------- > > (Updated 2010-08-13 10:12:44) > > > Review request for Default and Min Kyu Jeong. > > > Summary > ------- > > O3: Handle loads when the destination is the PC. > For loads that PC is the destination, check if the load > was mispredicted again when the value being loaded returns from memory > > > Diffs > ----- > > src/cpu/o3/iew.hh 3c48b2b3cb83 > src/cpu/o3/iew_impl.hh 3c48b2b3cb83 > src/cpu/o3/lsq_unit.hh 3c48b2b3cb83 > src/cpu/o3/lsq_unit_impl.hh 3c48b2b3cb83 > > Diff: http://reviews.m5sim.org/r/178/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
