> On 2010-08-14 00:45:14, Gabe Black wrote: > > The ISA parser is foundational for a LOT of code and shouldn't be changed > > unless it's absolutely necessary or the end goal itself. There are a lot of > > changes to it here, and without going through them it's likely most of them > > could/should be in the ISA description itself. Could you please explain why > > that can't be done and this has to go into the parser?
I agree, I think this issue should be dealt with in the O3 model and not in the ISA parser. Can't the O3 model just look at the dest reg(s) in the StaticInst and deal with it from there? - Steve ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/198/#review193 ----------------------------------------------------------- On 2010-08-13 10:17:15, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/198/ > ----------------------------------------------------------- > > (Updated 2010-08-13 10:17:15) > > > Review request for Default and Min Kyu Jeong. > > > Summary > ------- > > ARM: make predicated-false instruction to move data from a old register. > Thus a predicted flase instruction turns into a move from old register > to new register. This doesn't matter on the simple CPU, but is required > because of the physical registers on the o3 cpu. > > > Diffs > ----- > > src/arch/arm/isa/insts/misc.isa 3c48b2b3cb83 > src/arch/arm/isa/operands.isa 3c48b2b3cb83 > src/arch/arm/isa/templates/mem.isa 3c48b2b3cb83 > src/arch/arm/isa/templates/pred.isa 3c48b2b3cb83 > src/arch/isa_parser.py 3c48b2b3cb83 > > Diff: http://reviews.m5sim.org/r/198/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
