On Sun, Aug 15, 2010 at 6:07 PM, Min Kyu Jeong <[email protected]> wrote: > > > I needed to spit out a code that reads from a register, and writes to it > again. The thing is arch reg indices are renamed (reg renaming and shadow > reg file), so many structures are needed to be looked up to find a > previous/current physical register for the given arch reg name. These > indirections are handled in ISA-specific code and encapsulated, and the > operand section of the ISA description specifies which one to use.
I think we're thinking of these things on different levels... the operand registers are available via StaticInst::srcRegIdx() and destRegIdx(), and can be accessed via (for example) readIntReg() in o3/thread_context_impl.hh, none of which are ISA dependent. I don't see why you can't build on these calls to handle this entirely within the O3 model in an ISA-independent fashion (i.e., a way that would generalize to any ISA with universal predication, if we ever run into another one). Steve _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
