changeset 3f6413fc37a2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3f6413fc37a2
description:
sim: revamp unserialization procedure
Replace direct call to unserialize() on each SimObject with a pair of
calls for better control over initialization in both ckpt and non-ckpt
cases.
If restoring from a checkpoint, loadState(ckpt) is called on each
SimObject. The default implementation simply calls unserialize() if
there is a corresponding checkpoint section, so we get backward
compatibility for existing objects. However, objects can override
loadState() to get other behaviors, e.g., doing other programmed
initializations after unserialize(), or complaining if no checkpoint
section is found. (Note that the default warning for a missing
checkpoint section is now gone.)
If not restoring from a checkpoint, we call the new initState() method
on each SimObject instead. This provides a hook for state
initializations that are only required when *not* restoring from a
checkpoint.
Given this new framework, do some cleanup of LiveProcess subclasses
and X86System, which were (in some cases) emulating initState()
behavior in startup via a local flag or (in other cases) erroneously
doing initializations in startup() that clobbered state loaded earlier
by unserialize().
diffstat:
src/arch/alpha/process.cc | 26 +++++++++++++++++++++-----
src/arch/alpha/process.hh | 6 +++++-
src/arch/arm/process.cc | 4 +---
src/arch/mips/process.cc | 5 ++---
src/arch/mips/process.hh | 2 +-
src/arch/power/linux/process.cc | 4 ++--
src/arch/power/linux/process.hh | 2 +-
src/arch/power/process.cc | 7 +++----
src/arch/power/process.hh | 2 +-
src/arch/sparc/process.cc | 18 ++++++------------
src/arch/sparc/process.hh | 6 +++---
src/arch/x86/linux/system.cc | 4 ++--
src/arch/x86/linux/system.hh | 2 +-
src/arch/x86/process.cc | 14 ++++----------
src/arch/x86/process.hh | 4 ++--
src/arch/x86/system.cc | 5 +++--
src/arch/x86/system.hh | 2 +-
src/python/m5/simulate.py | 6 +++++-
src/python/swig/core.i | 5 ++++-
src/python/swig/pyobject.hh | 10 ++++++++--
src/python/swig/sim_object.i | 2 ++
src/sim/process.cc | 9 +++------
src/sim/process.hh | 5 +----
src/sim/serialize.cc | 15 ++-------------
src/sim/serialize.hh | 1 -
src/sim/sim_object.cc | 12 ++++++++++++
src/sim/sim_object.hh | 39 +++++++++++++++++++++++++++++++++++----
27 files changed, 131 insertions(+), 86 deletions(-)
diffs (truncated from 609 to 300 lines):
diff -r f5e86115a07a -r 3f6413fc37a2 src/arch/alpha/process.cc
--- a/src/arch/alpha/process.cc Tue Aug 17 05:17:06 2010 -0700
+++ b/src/arch/alpha/process.cc Tue Aug 17 05:17:06 2010 -0700
@@ -173,19 +173,35 @@
}
void
-AlphaLiveProcess::startup()
+AlphaLiveProcess::setupASNReg()
{
ThreadContext *tc = system->getThreadContext(contextIds[0]);
tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
+}
- if (checkpointRestored) {
- return;
- }
- Process::startup();
+void
+AlphaLiveProcess::loadState(Checkpoint *cp)
+{
+ LiveProcess::loadState(cp);
+ // need to set up ASN after unserialization since M5_pid value may
+ // come from checkpoint
+ setupASNReg();
+}
+
+
+void
+AlphaLiveProcess::initState()
+{
+ // need to set up ASN before further initialization since init
+ // will involve writing to virtual memory addresses
+ setupASNReg();
+
+ LiveProcess::initState();
argsInit(MachineBytes, VMPageSize);
+ ThreadContext *tc = system->getThreadContext(contextIds[0]);
tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
//Operate in user mode
tc->setMiscRegNoEffect(IPR_ICM, 0x18);
diff -r f5e86115a07a -r 3f6413fc37a2 src/arch/alpha/process.hh
--- a/src/arch/alpha/process.hh Tue Aug 17 05:17:06 2010 -0700
+++ b/src/arch/alpha/process.hh Tue Aug 17 05:17:06 2010 -0700
@@ -36,10 +36,14 @@
class AlphaLiveProcess : public LiveProcess
{
+ private:
+ void setupASNReg();
+
protected:
AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile);
- void startup();
+ void loadState(Checkpoint *cp);
+ void initState();
void argsInit(int intSize, int pageSize);
diff -r f5e86115a07a -r 3f6413fc37a2 src/arch/arm/process.cc
--- a/src/arch/arm/process.cc Tue Aug 17 05:17:06 2010 -0700
+++ b/src/arch/arm/process.cc Tue Aug 17 05:17:06 2010 -0700
@@ -76,6 +76,7 @@
void
ArmLiveProcess::startup()
{
+ LiveProcess::startup();
argsInit(MachineBytes, VMPageSize);
}
@@ -114,9 +115,6 @@
//We want 16 byte alignment
uint64_t align = 16;
- // Overloaded argsInit so that we can fine-tune for ARM architecture
- Process::startup();
-
// load object file into target memory
objFile->loadSections(initVirtMem);
diff -r f5e86115a07a -r 3f6413fc37a2 src/arch/mips/process.cc
--- a/src/arch/mips/process.cc Tue Aug 17 05:17:06 2010 -0700
+++ b/src/arch/mips/process.cc Tue Aug 17 05:17:06 2010 -0700
@@ -67,9 +67,9 @@
}
void
-MipsLiveProcess::startup()
+MipsLiveProcess::initState()
{
- Process::startup();
+ LiveProcess::initState();
argsInit<uint32_t>(VMPageSize);
}
@@ -79,7 +79,6 @@
MipsLiveProcess::argsInit(int pageSize)
{
int intSize = sizeof(IntType);
- Process::startup();
// load object file into target memory
objFile->loadSections(initVirtMem);
diff -r f5e86115a07a -r 3f6413fc37a2 src/arch/mips/process.hh
--- a/src/arch/mips/process.hh Tue Aug 17 05:17:06 2010 -0700
+++ b/src/arch/mips/process.hh Tue Aug 17 05:17:06 2010 -0700
@@ -45,7 +45,7 @@
protected:
MipsLiveProcess(LiveProcessParams * params, ObjectFile *objFile);
- void startup();
+ void initState();
template<class IntType>
void argsInit(int pageSize);
diff -r f5e86115a07a -r 3f6413fc37a2 src/arch/power/linux/process.cc
--- a/src/arch/power/linux/process.cc Tue Aug 17 05:17:06 2010 -0700
+++ b/src/arch/power/linux/process.cc Tue Aug 17 05:17:06 2010 -0700
@@ -432,9 +432,9 @@
}
void
-PowerLinuxProcess::startup()
+PowerLinuxProcess::initState()
{
- PowerLiveProcess::startup();
+ PowerLiveProcess::initState();
}
PowerISA::IntReg
diff -r f5e86115a07a -r 3f6413fc37a2 src/arch/power/linux/process.hh
--- a/src/arch/power/linux/process.hh Tue Aug 17 05:17:06 2010 -0700
+++ b/src/arch/power/linux/process.hh Tue Aug 17 05:17:06 2010 -0700
@@ -44,7 +44,7 @@
virtual SyscallDesc* getDesc(int callnum);
- void startup();
+ void initState();
PowerISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
void setSyscallArg(ThreadContext *tc, int i, PowerISA::IntReg val);
diff -r f5e86115a07a -r 3f6413fc37a2 src/arch/power/process.cc
--- a/src/arch/power/process.cc Tue Aug 17 05:17:06 2010 -0700
+++ b/src/arch/power/process.cc Tue Aug 17 05:17:06 2010 -0700
@@ -63,8 +63,10 @@
}
void
-PowerLiveProcess::startup()
+PowerLiveProcess::initState()
{
+ Process::initState();
+
argsInit(MachineBytes, VMPageSize);
}
@@ -83,9 +85,6 @@
//We want 16 byte alignment
uint64_t align = 16;
- // Overloaded argsInit so that we can fine-tune for POWER architecture
- Process::startup();
-
// load object file into target memory
objFile->loadSections(initVirtMem);
diff -r f5e86115a07a -r 3f6413fc37a2 src/arch/power/process.hh
--- a/src/arch/power/process.hh Tue Aug 17 05:17:06 2010 -0700
+++ b/src/arch/power/process.hh Tue Aug 17 05:17:06 2010 -0700
@@ -46,7 +46,7 @@
protected:
PowerLiveProcess(LiveProcessParams * params, ObjectFile *objFile);
- void startup();
+ void initState();
public:
void argsInit(int intSize, int pageSize);
diff -r f5e86115a07a -r 3f6413fc37a2 src/arch/sparc/process.cc
--- a/src/arch/sparc/process.cc Tue Aug 17 05:17:06 2010 -0700
+++ b/src/arch/sparc/process.cc Tue Aug 17 05:17:06 2010 -0700
@@ -111,9 +111,9 @@
}
void
-SparcLiveProcess::startup()
+SparcLiveProcess::initState()
{
- Process::startup();
+ LiveProcess::initState();
ThreadContext *tc = system->getThreadContext(contextIds[0]);
//From the SPARC ABI
@@ -157,12 +157,9 @@
}
void
-Sparc32LiveProcess::startup()
+Sparc32LiveProcess::initState()
{
- if (checkpointRestored)
- return;
-
- SparcLiveProcess::startup();
+ SparcLiveProcess::initState();
ThreadContext *tc = system->getThreadContext(contextIds[0]);
//The process runs in user mode with 32 bit addresses
@@ -172,12 +169,9 @@
}
void
-Sparc64LiveProcess::startup()
+Sparc64LiveProcess::initState()
{
- if (checkpointRestored)
- return;
-
- SparcLiveProcess::startup();
+ SparcLiveProcess::initState();
ThreadContext *tc = system->getThreadContext(contextIds[0]);
//The process runs in user mode
diff -r f5e86115a07a -r 3f6413fc37a2 src/arch/sparc/process.hh
--- a/src/arch/sparc/process.hh Tue Aug 17 05:17:06 2010 -0700
+++ b/src/arch/sparc/process.hh Tue Aug 17 05:17:06 2010 -0700
@@ -52,7 +52,7 @@
SparcLiveProcess(LiveProcessParams * params,
ObjectFile *objFile, Addr _StackBias);
- void startup();
+ void initState();
template<class IntType>
void argsInit(int pageSize);
@@ -87,7 +87,7 @@
mmap_start = mmap_end = 0x70000000;
}
- void startup();
+ void initState();
public:
@@ -115,7 +115,7 @@
mmap_start = mmap_end = 0xfffff80000000000ULL;
}
- void startup();
+ void initState();
public:
diff -r f5e86115a07a -r 3f6413fc37a2 src/arch/x86/linux/system.cc
--- a/src/arch/x86/linux/system.cc Tue Aug 17 05:17:06 2010 -0700
+++ b/src/arch/x86/linux/system.cc Tue Aug 17 05:17:06 2010 -0700
@@ -59,9 +59,9 @@
}
void
-LinuxX86System::startup()
+LinuxX86System::initState()
{
- X86System::startup();
+ X86System::initState();
// The location of the real mode data structure.
const Addr realModeData = 0x90200;
diff -r f5e86115a07a -r 3f6413fc37a2 src/arch/x86/linux/system.hh
--- a/src/arch/x86/linux/system.hh Tue Aug 17 05:17:06 2010 -0700
+++ b/src/arch/x86/linux/system.hh Tue Aug 17 05:17:06 2010 -0700
@@ -58,7 +58,7 @@
LinuxX86System(Params *p);
~LinuxX86System();
- void startup();
+ void initState();
};
#endif
diff -r f5e86115a07a -r 3f6413fc37a2 src/arch/x86/process.cc
--- a/src/arch/x86/process.cc Tue Aug 17 05:17:06 2010 -0700
+++ b/src/arch/x86/process.cc Tue Aug 17 05:17:06 2010 -0700
@@ -157,12 +157,9 @@
}
void
-X86_64LiveProcess::startup()
+X86_64LiveProcess::initState()
{
- LiveProcess::startup();
-
- if (checkpointRestored)
- return;
+ X86LiveProcess::initState();
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