----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/200/#review270 -----------------------------------------------------------
src/cpu/o3/fetch_impl.hh <http://reviews.m5sim.org/r/200/#comment405> Fair enough, but it's how all the serial numbers are printed in the file. if we want to change it we should probably have a diff that changes them all. - Ali On 2010-08-13 10:18:10, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/200/ > ----------------------------------------------------------- > > (Updated 2010-08-13 10:18:10) > > > Review request for Default and Min Kyu Jeong. > > > Summary > ------- > > O3: Skipping mem-order violation check for uncachable loads. > Uncachable load is not executed until it reaches the head of the ROB, > hence cannot cause one. > > > Diffs > ----- > > src/cpu/o3/fetch_impl.hh 3c48b2b3cb83 > src/cpu/o3/iew_impl.hh 3c48b2b3cb83 > src/cpu/o3/lsq_unit_impl.hh 3c48b2b3cb83 > > Diff: http://reviews.m5sim.org/r/200/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
