> I still don't think it's a great idea, but I'm outvoted so go ahead. I missed most of this conversation since I've been traveling, but just for the record (and to make Gabe feel more lonely) I'll weigh in on Nate & Ali's side. Predication is a feature like delay slots, unaligned accesses, or self-modifying code that some ISAs have and some don't, and basically the CPU models have to support the superset of the features of the ISAs we support.
In particular, given that both Gabe and I feel that the ISA parser changes in another patch are a misguided attempt to push the complexity of handling register-renamed predicated operations into a layer where they don't belong, I think you have to agree that the complexity is going to end up somewhere, and I think that the CPU model is the place for that. In terms of performance impact, I'd be happy to see a static ISA 'HasPredication' flag that allows all the predication tests to be left out at compile time for ISAs that don't use it, but that's an optimization not a requirement. Steve _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
