changeset aa32d1398dfd in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=aa32d1398dfd
description:
ARM: Exclusive accesses must be double word aligned
diffstat:
src/arch/arm/isa/insts/ldr.isa | 4 +++-
src/arch/arm/isa/insts/str.isa | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diffs (30 lines):
diff -r 24b18c320b66 -r aa32d1398dfd src/arch/arm/isa/insts/ldr.isa
--- a/src/arch/arm/isa/insts/ldr.isa Mon Aug 23 11:18:40 2010 -0500
+++ b/src/arch/arm/isa/insts/ldr.isa Mon Aug 23 11:18:40 2010 -0500
@@ -206,7 +206,9 @@
# Add memory request flags where necessary
if self.flavor == "exclusive":
self.memFlags.append("Request::LLSC")
- self.memFlags.append("ArmISA::TLB::AlignWord")
+ self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
+ else:
+ self.memFlags.append("ArmISA::TLB::AlignWord")
# Disambiguate the class name for different flavors of loads
if self.flavor != "normal":
diff -r 24b18c320b66 -r aa32d1398dfd src/arch/arm/isa/insts/str.isa
--- a/src/arch/arm/isa/insts/str.isa Mon Aug 23 11:18:40 2010 -0500
+++ b/src/arch/arm/isa/insts/str.isa Mon Aug 23 11:18:40 2010 -0500
@@ -225,9 +225,11 @@
self.Name = self.nameFunc(self.post, self.add, self.writeback)
# Add memory request flags where necessary
- self.memFlags.append("ArmISA::TLB::AlignWord")
if self.flavor == "exclusive":
self.memFlags.append("Request::LLSC")
+ self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
+ else:
+ self.memFlags.append("ArmISA::TLB::AlignWord")
# Disambiguate the class name for different flavors of stores
if self.flavor != "normal":
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