changeset aca917ca1ad5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=aca917ca1ad5
description:
ALPHA: The previous O3 patch causes a slight stats change with fullsys.
diffstat:
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout | 14 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 2000
+++++----
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout | 14 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 948 ++--
4 files changed, 1487 insertions(+), 1489 deletions(-)
diffs (truncated from 3675 to 300 lines):
diff -r 1a0ab2308bbe -r aca917ca1ad5
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Mon Aug
23 11:18:42 2010 -0500
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Mon Aug
23 11:18:42 2010 -0500
@@ -1,5 +1,3 @@
-Redirecting stdout to
build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
-Redirecting stderr to
build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,13 +5,13 @@
All Rights Reserved
-M5 compiled Jun 16 2010 10:39:13
-M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats
-M5 started Jun 16 2010 10:40:27
-M5 executing on phenom
+M5 compiled Aug 3 2010 18:29:42
+M5 revision 75205c286109 7549 default qtip tip
ext/memorderviolation_uncached.patch
+M5 started Aug 3 2010 18:34:19
+M5 executing on harpertown2
command line: build/ALPHA_FS/m5.fast -d
build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re
tests/run.py
build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /root/ali/dist/system/m5_system_2.0b3/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 125751000
-Exiting @ tick 1907689250500 because m5_exit instruction encountered
+Exiting @ tick 1908681362500 because m5_exit instruction encountered
diff -r 1a0ab2308bbe -r aca917ca1ad5
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Mon Aug 23 11:18:42 2010 -0500
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Mon Aug 23 11:18:42 2010 -0500
@@ -1,447 +1,449 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 198866 #
Simulator instruction rate (inst/s)
-host_mem_usage 278256 #
Number of bytes of host memory used
-host_seconds 282.46 #
Real time elapsed on the host
-host_tick_rate 6753860070 #
Simulator tick rate (ticks/s)
+host_inst_rate 149891 #
Simulator instruction rate (inst/s)
+host_mem_usage 287008 #
Number of bytes of host memory used
+host_seconds 374.37 #
Real time elapsed on the host
+host_tick_rate 5098345411 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 56171530 #
Number of instructions simulated
-sim_seconds 1.907689 #
Number of seconds simulated
-sim_ticks 1907689250500 #
Number of ticks simulated
+sim_insts 56115151 #
Number of instructions simulated
+sim_seconds 1.908681 #
Number of seconds simulated
+sim_ticks 1908681362500 #
Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.BTBHits 5124021 #
Number of BTB hits
-system.cpu0.BPredUnit.BTBLookups 9548324 #
Number of BTB lookups
-system.cpu0.BPredUnit.RASInCorrect 25931 #
Number of incorrect RAS predictions.
-system.cpu0.BPredUnit.condIncorrect 576265 #
Number of conditional branches incorrect
-system.cpu0.BPredUnit.condPredicted 8953132 #
Number of conditional branches predicted
-system.cpu0.BPredUnit.lookups 10665388 #
Number of BP lookups
-system.cpu0.BPredUnit.usedRAS 730260 #
Number of times the RAS was used to get a target.
-system.cpu0.commit.COM:branches 6306789 #
Number of branches committed
-system.cpu0.commit.COM:bw_lim_events 727470 #
number cycles where commit BW limit reached
+system.cpu0.BPredUnit.BTBHits 6470772 #
Number of BTB hits
+system.cpu0.BPredUnit.BTBLookups 12459992 #
Number of BTB lookups
+system.cpu0.BPredUnit.RASInCorrect 36652 #
Number of incorrect RAS predictions.
+system.cpu0.BPredUnit.condIncorrect 761921 #
Number of conditional branches incorrect
+system.cpu0.BPredUnit.condPredicted 11628226 #
Number of conditional branches predicted
+system.cpu0.BPredUnit.lookups 13936368 #
Number of BP lookups
+system.cpu0.BPredUnit.usedRAS 988790 #
Number of times the RAS was used to get a target.
+system.cpu0.commit.COM:branches 8127927 #
Number of branches committed
+system.cpu0.commit.COM:bw_lim_events 948928 #
number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited 0 #
number of insts not committed due to BW limits
-system.cpu0.commit.COM:committed_per_cycle::samples 73665183
# Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::mean 0.571097
# Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::stdev 1.330919
# Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::samples 96210525
# Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::mean 0.559994
# Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::stdev 1.324793
# Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00%
0.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::0 55454240 75.28%
75.28% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::1 8064036 10.95%
86.23% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::2 4660922 6.33%
92.55% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::3 2129949 2.89%
95.44% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::4 1559149 2.12%
97.56% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::5 477103 0.65%
98.21% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::6 293859 0.40%
98.61% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::7 298455 0.41%
99.01% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::8 727470 0.99%
100.00% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::0 73079830 75.96%
75.96% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::1 10159186 10.56%
86.52% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::2 5793964 6.02%
92.54% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::3 2862156 2.97%
95.51% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::4 1992019 2.07%
97.59% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::5 630403 0.66%
98.24% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::6 376031 0.39%
98.63% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::7 368008 0.38%
99.01% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::8 948928 0.99%
100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00%
100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value 0
# Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value 8
# Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::total 73665183
# Number of insts commited each cycle
-system.cpu0.commit.COM:count 42069937 #
Number of instructions committed
-system.cpu0.commit.COM:loads 6784715 #
Number of loads committed
-system.cpu0.commit.COM:membars 161083 #
Number of memory barriers committed
-system.cpu0.commit.COM:refs 11506692 #
Number of memory references committed
+system.cpu0.commit.COM:committed_per_cycle::total 96210525
# Number of insts commited each cycle
+system.cpu0.commit.COM:count 53877339 #
Number of instructions committed
+system.cpu0.commit.COM:loads 8834098 #
Number of loads committed
+system.cpu0.commit.COM:membars 219262 #
Number of memory barriers committed
+system.cpu0.commit.COM:refs 14863142 #
Number of memory references committed
system.cpu0.commit.COM:swp_count 0 #
Number of s/w prefetches committed
-system.cpu0.commit.branchMispredicts 548150 #
The number of times a branch was mispredicted
-system.cpu0.commit.commitCommittedInsts 42069937 #
The number of committed instructions
-system.cpu0.commit.commitNonSpecStalls 486094 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.commitSquashedInsts 6570892 #
The number of squashed insts skipped by commit
-system.cpu0.committedInsts 39732534 #
Number of Instructions Simulated
-system.cpu0.committedInsts_total 39732534 #
Number of Instructions Simulated
-system.cpu0.cpi 2.659989 #
CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.659989 #
CPI: Total CPI of All Threads
-system.cpu0.dcache.LoadLockedReq_accesses::0 157022
# number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 157022
# number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15337.494650
# average LoadLockedReq miss latency
+system.cpu0.commit.branchMispredicts 723488 #
The number of times a branch was mispredicted
+system.cpu0.commit.commitCommittedInsts 53877339 #
The number of committed instructions
+system.cpu0.commit.commitNonSpecStalls 642718 #
The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.commitSquashedInsts 8676299 #
The number of squashed insts skipped by commit
+system.cpu0.committedInsts 50753913 #
Number of Instructions Simulated
+system.cpu0.committedInsts_total 50753913 #
Number of Instructions Simulated
+system.cpu0.cpi 2.598475 #
CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.598475 #
CPI: Total CPI of All Threads
+system.cpu0.dcache.LoadLockedReq_accesses::0 205122
# number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 205122
# number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15332.515478
# average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf
# average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf
# average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11734.631539
# average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits::0 143004 #
number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 143004
# number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency 215001000
# number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.089274
# miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses::0 14018
# number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 14018
# number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_hits 3542
# number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 122932000
# number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.066717
# mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11584.904538
# average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits::0 183317 #
number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 183317
# number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency 334325500
# number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106303
# miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses::0 21805
# number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 21805
# number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_hits 4992
# number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 194777000
# number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.081966
# mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf
# mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf
# mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses 10476
# number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses::0 6796922 #
number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 6796922
# number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 28045.834026
# average ReadReq miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_misses 16813
# number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses::0 8824783 #
number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 8824783
# number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 24295.121423
# average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf
# average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total inf
# average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27628.067292
# average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23079.908159
# average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf
# average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits::0 5780701 #
number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 5780701 #
number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 28500765500 #
number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate::0 0.149512 #
miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses::0 1016221 #
number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1016221 #
number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_hits 272772 #
number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_miss_latency 20540059000
# number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.109380
# mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_hits::0 7389262 #
number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 7389262 #
number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency 34876157000 #
number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate::0 0.162669 #
miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses::0 1435521 #
number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 1435521 #
number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_hits 389370 #
number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_miss_latency 24145069000
# number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.118547
# mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf
# mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf
# mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses 743449 #
number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639143000
# number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses::0 165236
# number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 165236
# number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 54890.406800
# average StoreCondReq miss latency
+system.cpu0.dcache.ReadReq_mshr_misses 1046151 #
number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 922902000
# number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_accesses::0 210601
# number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 210601
# number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 55488.433658
# average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf
# average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf
# average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51890.406800
# average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits::0 147119 #
number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 147119
# number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency 994449500
# number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate::0 0.109643
# miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses::0 18117 #
number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 18117
# number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency 940098500
# number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.109643
# mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52488.433658
# average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_hits::0 182459 #
number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 182459
# number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_latency 1561555500
# number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_rate::0 0.133627
# miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses::0 28142 #
number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 28142
# number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1477129500
# number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.133627
# mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf
# mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf
# mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_misses 18117
# number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses::0 4544003 #
number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 4544003
# number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 48917.848661
# average WriteReq miss latency
+system.cpu0.dcache.StoreCondReq_mshr_misses 28142
# number of StoreCondReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses::0 5803460 #
number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 5803460
# number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 48954.080777
# average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf
# average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total inf
# average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 54316.339615
# average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 54100.546465
# average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf
# average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits::0 2781940 #
number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 2781940 #
number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 86196331165 #
number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate::0 0.387778 #
miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses::0 1762063 #
number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1762063 #
number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_hits 1458631 #
number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_miss_latency 16481315562
# number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.066776
# mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_hits::0 3719396 #
number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 3719396 #
number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 102023437400 #
number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate::0 0.359107 #
miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses::0 2084064 #
number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 2084064 #
number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_hits 1707487 #
number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_miss_latency 20373021486
# number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.064888
# mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf
# mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf
# mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 303432 #
number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1049908497
# number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9537.404034
# average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 9.143990 #
Average number of references to valid blocks.
-system.cpu0.dcache.blocked::no_mshrs 120871 #
number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 #
number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs 1152795563
# number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
+system.cpu0.dcache.WriteReq_mshr_misses 376577 #
number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1266172497
# number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9947.496514
# average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 21500
# average number of cycles each access was blocked
+system.cpu0.dcache.avg_refs 8.716740 #
Average number of references to valid blocks.
+system.cpu0.dcache.blocked::no_mshrs 127068 #
number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 7 #
number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_mshrs 1264008487
# number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 150500
# number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu0.dcache.demand_accesses::0 11340925 #
number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::0 14628243 #
number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1 0 #
number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 11340925 #
number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency::0 41283.431307
# average overall miss latency
+system.cpu0.dcache.demand_accesses::total 14628243 #
number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency::0 38896.516038
# average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::1 inf
# average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total inf
# average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 35363.498394
# average overall mshr miss latency
-system.cpu0.dcache.demand_hits::0 8562641 #
number of demand (read+write) hits
+system.cpu0.dcache.demand_avg_mshr_miss_latency 31290.654634
# average overall mshr miss latency
+system.cpu0.dcache.demand_hits::0 11108658 #
number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1 0 #
number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 8562641 #
number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 114697096665 #
number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate::0 0.244979 #
miss rate for demand accesses
+system.cpu0.dcache.demand_hits::total 11108658 #
number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 136899594400 #
number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate::0 0.240602 #
miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1 no_value #
miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total no_value
# miss rate for demand accesses
-system.cpu0.dcache.demand_misses::0 2778284 #
number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::0 3519585 #
number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1 0 #
number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 2778284 #
number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 1731403 #
number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 37021374562
# number of demand (read+write) MSHR miss cycles
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