changeset aec271db42c9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=aec271db42c9
description:
mem: fix functional accesses to deal with coherence change
We can't just obliviously return the first valid cache block
we find any more... see comments for details.
diffstat:
src/mem/bridge.cc | 4 +++-
src/mem/cache/cache_impl.hh | 29 ++++++++++++++++++++++++++---
src/mem/packet.cc | 1 -
3 files changed, 29 insertions(+), 5 deletions(-)
diffs (77 lines):
diff -r aa8fd8f6a495 -r aec271db42c9 src/mem/bridge.cc
--- a/src/mem/bridge.cc Thu Sep 09 14:40:18 2010 -0400
+++ b/src/mem/bridge.cc Thu Sep 09 14:40:19 2010 -0400
@@ -325,8 +325,10 @@
pkt->pushLabel(name());
for (i = sendQueue.begin(); i != sendQueue.end(); ++i) {
- if (pkt->checkFunctional((*i)->pkt))
+ if (pkt->checkFunctional((*i)->pkt)) {
+ pkt->makeResponse();
return;
+ }
}
pkt->popLabel();
diff -r aa8fd8f6a495 -r aec271db42c9 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Thu Sep 09 14:40:18 2010 -0400
+++ b/src/mem/cache/cache_impl.hh Thu Sep 09 14:40:19 2010 -0400
@@ -759,21 +759,44 @@
{
Addr blk_addr = blockAlign(pkt->getAddr());
BlkType *blk = tags->findBlock(pkt->getAddr());
+ MSHR *mshr = mshrQueue.findMatch(blk_addr);
pkt->pushLabel(name());
CacheBlkPrintWrapper cbpw(blk);
- bool done =
- (blk && pkt->checkFunctional(&cbpw, blk_addr, blkSize, blk->data))
+
+ // Note that just because an L2/L3 has valid data doesn't mean an
+ // L1 doesn't have a more up-to-date modified copy that still
+ // needs to be found. As a result we always update the request if
+ // we have it, but only declare it satisfied if we are the owner.
+
+ // see if we have data at all (owned or otherwise)
+ bool have_data = blk && blk->isValid()
+ && pkt->checkFunctional(&cbpw, blk_addr, blkSize, blk->data);
+
+ // data we have is dirty if marked as such or if valid & ownership
+ // pending due to outstanding UpgradeReq
+ bool have_dirty =
+ have_data && (blk->isDirty() ||
+ (mshr && mshr->inService && mshr->isPendingDirty()));
+
+ bool done = have_dirty
|| incomingPort->checkFunctional(pkt)
|| mshrQueue.checkFunctional(pkt, blk_addr)
|| writeBuffer.checkFunctional(pkt, blk_addr)
|| otherSidePort->checkFunctional(pkt);
+ DPRINTF(Cache, "functional %s %x %s%s%s\n",
+ pkt->cmdString(), pkt->getAddr(),
+ (blk && blk->isValid()) ? "valid " : "",
+ have_data ? "data " : "", done ? "done " : "");
+
// We're leaving the cache, so pop cache->name() label
pkt->popLabel();
- if (!done) {
+ if (done) {
+ pkt->makeResponse();
+ } else {
otherSidePort->sendFunctional(pkt);
}
}
diff -r aa8fd8f6a495 -r aec271db42c9 src/mem/packet.cc
--- a/src/mem/packet.cc Thu Sep 09 14:40:18 2010 -0400
+++ b/src/mem/packet.cc Thu Sep 09 14:40:19 2010 -0400
@@ -179,7 +179,6 @@
if (func_start >= val_start && func_end <= val_end) {
allocate();
memcpy(getPtr<uint8_t>(), data + offset, getSize());
- makeResponse();
return true;
} else {
// In this case the timing packet only partially satisfies
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