changeset cc222ba29079 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cc222ba29079
description:
cache: fail SC when invalidated while waiting for bus
Corrects an oversight in cset f97b62be544f. The fix there only
failed queued SCUpgradeReq packets that encountered an
invalidation, which meant that the upgrade had to reach the L2
cache. To handle pending requests in the L1 we must similarly
fail StoreCondReq packets too.
diffstat:
src/mem/cache/cache_impl.hh | 14 ++++++++------
src/mem/cache/mshr.cc | 8 +++++++-
src/mem/packet.cc | 4 ++++
src/mem/packet.hh | 1 +
4 files changed, 20 insertions(+), 7 deletions(-)
diffs (82 lines):
diff -r aec271db42c9 -r cc222ba29079 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Thu Sep 09 14:40:19 2010 -0400
+++ b/src/mem/cache/cache_impl.hh Thu Sep 09 14:40:19 2010 -0400
@@ -900,9 +900,10 @@
assert(!target->pkt->req->isUncacheable());
missLatency[target->pkt->cmdToIndex()][0/*pkt->req->threadId()*/] +=
completion_time - target->recvTime;
- } else if (target->pkt->cmd == MemCmd::StoreCondReq &&
- pkt->cmd == MemCmd::UpgradeFailResp) {
+ } else if (pkt->cmd == MemCmd::UpgradeFailResp) {
// failed StoreCond upgrade
+ assert(target->pkt->cmd == MemCmd::StoreCondReq ||
+ target->pkt->cmd == MemCmd::StoreCondFailReq);
completion_time = tags->getHitLatency() + pkt->finishTime;
target->pkt->req->setExtraData(0);
} else {
@@ -1443,10 +1444,11 @@
PacketPtr tgt_pkt = mshr->getTarget()->pkt;
PacketPtr pkt = NULL;
- if (tgt_pkt->cmd == MemCmd::SCUpgradeFailReq) {
- // SCUpgradeReq saw invalidation while queued in MSHR, so now
- // that we are getting around to processing it, just treat it
- // as if we got a failure response
+ if (tgt_pkt->cmd == MemCmd::SCUpgradeFailReq ||
+ tgt_pkt->cmd == MemCmd::StoreCondFailReq) {
+ // SCUpgradeReq or StoreCondReq saw invalidation while queued
+ // in MSHR, so now that we are getting around to processing
+ // it, just treat it as if we got a failure response
pkt = new Packet(tgt_pkt);
pkt->cmd = MemCmd::UpgradeFailResp;
pkt->senderState = mshr;
diff -r aec271db42c9 -r cc222ba29079 src/mem/cache/mshr.cc
--- a/src/mem/cache/mshr.cc Thu Sep 09 14:40:19 2010 -0400
+++ b/src/mem/cache/mshr.cc Thu Sep 09 14:40:19 2010 -0400
@@ -72,7 +72,10 @@
needsExclusive = true;
}
- if (pkt->isUpgrade()) {
+ // StoreCondReq is effectively an upgrade if it's in an MSHR
+ // since it would have been failed already if we didn't have a
+ // read-only copy
+ if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
hasUpgrade = true;
}
}
@@ -98,6 +101,9 @@
} else if (pkt->cmd == MemCmd::SCUpgradeReq) {
pkt->cmd = MemCmd::SCUpgradeFailReq;
DPRINTF(Cache, "Replacing SCUpgradeReq with SCUpgradeFailReq\n");
+ } else if (pkt->cmd == MemCmd::StoreCondReq) {
+ pkt->cmd = MemCmd::StoreCondFailReq;
+ DPRINTF(Cache, "Replacing StoreCondReq with StoreCondFailReq\n");
}
}
diff -r aec271db42c9 -r cc222ba29079 src/mem/packet.cc
--- a/src/mem/packet.cc Thu Sep 09 14:40:19 2010 -0400
+++ b/src/mem/packet.cc Thu Sep 09 14:40:19 2010 -0400
@@ -123,6 +123,10 @@
{ SET6(IsWrite, NeedsExclusive, IsLlsc,
IsRequest, NeedsResponse, HasData),
StoreCondResp, "StoreCondReq" },
+ /* StoreCondFailReq: generates failing StoreCondResp ASAP */
+ { SET6(IsWrite, NeedsExclusive, IsLlsc,
+ IsRequest, NeedsResponse, HasData),
+ StoreCondResp, "StoreCondFailReq" },
/* StoreCondResp */
{ SET4(IsWrite, NeedsExclusive, IsLlsc, IsResponse),
InvalidCmd, "StoreCondResp" },
diff -r aec271db42c9 -r cc222ba29079 src/mem/packet.hh
--- a/src/mem/packet.hh Thu Sep 09 14:40:19 2010 -0400
+++ b/src/mem/packet.hh Thu Sep 09 14:40:19 2010 -0400
@@ -90,6 +90,7 @@
ReadExResp,
LoadLockedReq,
StoreCondReq,
+ StoreCondFailReq, // Failed StoreCondReq in MSHR (never sent)
StoreCondResp,
SwapReq,
SwapResp,
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