changeset f6e808dd36af in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=f6e808dd36af description: stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
diffstat: tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini | 2 +- tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr | 3 + tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout | 13 +- tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 659 +- tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini | 4 +- tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr | 3 + tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout | 13 +- tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt | 183 +- tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/00.gzip/ref/arm/linux/simple-timing/simout | 12 +- tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt | 181 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini | 2 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/simout | 14 +- tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 621 +- tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini | 4 +- tests/long/00.gzip/ref/sparc/linux/simple-timing/simout | 14 +- tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt | 195 +- tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini | 2 +- tests/long/00.gzip/ref/x86/linux/simple-timing/simout | 14 +- tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt | 179 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini | 13 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout | 19 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 2011 +++++---- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini | 13 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout | 17 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 1000 ++-- tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/10.mcf/ref/arm/linux/simple-timing/simout | 12 +- tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt | 155 +- tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini | 6 +- tests/long/10.mcf/ref/sparc/linux/simple-timing/simout | 14 +- tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt | 145 +- tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini | 2 +- tests/long/10.mcf/ref/x86/linux/simple-timing/simout | 14 +- tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt | 189 +- tests/long/20.parser/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/20.parser/ref/arm/linux/simple-timing/simout | 12 +- tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt | 209 +- tests/long/20.parser/ref/x86/linux/simple-timing/config.ini | 2 +- tests/long/20.parser/ref/x86/linux/simple-timing/simout | 14 +- tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt | 191 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini | 2 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr | 3 + tests/long/30.eon/ref/alpha/tru64/o3-timing/simout | 13 +- tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 663 +- tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini | 4 +- tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr | 3 + tests/long/30.eon/ref/alpha/tru64/simple-timing/simout | 13 +- tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt | 141 +- tests/long/30.eon/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/30.eon/ref/arm/linux/simple-timing/simout | 12 +- tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt | 147 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini | 2 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr | 3 + tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout | 13 +- tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 658 +- tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini | 4 +- tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr | 3 + tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout | 13 +- tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt | 160 +- tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout | 12 +- tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt | 181 +- tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini | 2 +- tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr | 3 + tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout | 13 +- tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt | 269 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini | 2 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr | 3 + tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout | 13 +- tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 679 +- tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini | 4 +- tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr | 3 + tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout | 13 +- tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt | 207 +- tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/50.vortex/ref/arm/linux/simple-timing/simout | 12 +- tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt | 207 +- tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini | 4 +- tests/long/50.vortex/ref/sparc/linux/simple-timing/simout | 14 +- tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt | 223 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini | 2 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr | 3 + tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout | 13 +- tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 663 +- tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini | 4 +- tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr | 3 + tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout | 13 +- tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt | 185 +- tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/60.bzip2/ref/arm/linux/simple-timing/simout | 12 +- tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt | 185 +- tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini | 2 +- tests/long/60.bzip2/ref/x86/linux/simple-timing/simout | 14 +- tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt | 185 +- tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini | 2 +- tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr | 3 + tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout | 16 +- tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 184 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini | 2 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr | 3 + tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout | 18 +- tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt | 648 +- tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini | 4 +- tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr | 3 + tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout | 16 +- tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt | 98 +- tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini | 2 +- tests/long/70.twolf/ref/arm/linux/simple-timing/simout | 16 +- tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt | 90 +- tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini | 4 +- tests/long/70.twolf/ref/sparc/linux/simple-timing/simout | 16 +- tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt | 95 +- tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini | 2 +- tests/long/70.twolf/ref/x86/linux/simple-timing/simout | 18 +- tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt | 89 +- tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout | 14 +- tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt | 173 +- tests/quick/00.hello/ref/alpha/linux/o3-timing/simout | 14 +- tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt | 501 +- tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini | 2 +- tests/quick/00.hello/ref/alpha/linux/simple-timing/simout | 14 +- tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt | 87 +- tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout | 14 +- tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 484 +- tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini | 2 +- tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout | 14 +- tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt | 83 +- tests/quick/00.hello/ref/mips/linux/inorder-timing/simout | 14 +- tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt | 209 +- tests/quick/00.hello/ref/mips/linux/o3-timing/simout | 14 +- tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | 461 +- tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini | 2 +- tests/quick/00.hello/ref/mips/linux/simple-timing/simout | 14 +- tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt | 87 +- tests/quick/00.hello/ref/power/linux/o3-timing/simerr | 2 +- tests/quick/00.hello/ref/power/linux/o3-timing/simout | 14 +- tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt | 293 +- tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini | 2 +- tests/quick/00.hello/ref/sparc/linux/simple-timing/simout | 14 +- tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt | 93 +- tests/quick/00.hello/ref/x86/linux/simple-timing/simout | 14 +- tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt | 87 +- tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout | 14 +- tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt | 840 ++-- tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout | 14 +- tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt | 385 +- tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini | 2 +- tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout | 14 +- tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt | 87 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini | 13 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout | 17 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt | 241 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini | 13 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout | 17 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt | 132 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini | 13 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout | 21 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 1126 ++-- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini | 13 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout | 19 +- tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 580 +- tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini | 2 +- tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout | 12 +- tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt | 85 +- tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini | 8 +- tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr | 4 + tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout | 10 +- tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt | 123 +- tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini | 8 +- tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout | 10 +- tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt | 657 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout | 12 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 726 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini | 2 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout | 10 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt | 50 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini | 2 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout | 12 +- tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt | 200 +- tests/quick/50.memtest/ref/alpha/linux/memtest/simerr | 146 +- tests/quick/50.memtest/ref/alpha/linux/memtest/simout | 14 +- tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt | 1572 +++--- 183 files changed, 11250 insertions(+), 11202 deletions(-) diffs (truncated from 32641 to 300 lines): diff -r cc222ba29079 -r f6e808dd36af tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Thu Sep 09 14:40:19 2010 -0400 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Thu Sep 09 14:40:19 2010 -0400 @@ -353,7 +353,7 @@ [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr diff -r cc222ba29079 -r f6e808dd36af tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr Thu Sep 09 14:40:19 2010 -0400 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr Thu Sep 09 14:40:19 2010 -0400 @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff -r cc222ba29079 -r f6e808dd36af tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Thu Sep 09 14:40:19 2010 -0400 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Thu Sep 09 14:40:19 2010 -0400 @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simerr +Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +7,11 @@ All Rights Reserved -M5 compiled Jun 6 2010 03:04:38 -M5 revision ba1a0193c050 7448 default tip -M5 started Jun 6 2010 03:24:00 +M5 compiled Aug 26 2010 11:51:59 +M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix +M5 started Aug 26 2010 11:52:05 M5 executing on zizzer -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -46,3 +46,4 @@ Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! +Exiting @ tick 169506496500 because target called exit() diff -r cc222ba29079 -r f6e808dd36af tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Thu Sep 09 14:40:19 2010 -0400 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Thu Sep 09 14:40:19 2010 -0400 @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 217525 # Simulator instruction rate (inst/s) -host_mem_usage 207124 # Number of bytes of host memory used -host_seconds 2599.94 # Real time elapsed on the host -host_tick_rate 64460403 # Simulator tick rate (ticks/s) +host_inst_rate 178555 # Simulator instruction rate (inst/s) +host_mem_usage 207544 # Number of bytes of host memory used +host_seconds 3167.39 # Real time elapsed on the host +host_tick_rate 53516139 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.167593 # Number of seconds simulated -sim_ticks 167593085500 # Number of ticks simulated +sim_seconds 0.169506 # Number of seconds simulated +sim_ticks 169506496500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 63922842 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 71487962 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 180 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 4121924 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 70504427 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 76440051 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1674270 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 64068954 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 71556079 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 188 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 4120910 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 70589657 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 76519042 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1672225 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 18448626 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 19702213 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 323575021 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.860023 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.297815 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 327417755 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.838193 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.277454 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 107931872 33.36% 33.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 101513205 31.37% 64.73% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 37265964 11.52% 76.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 10166735 3.14% 79.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 11290718 3.49% 82.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 21721468 6.71% 89.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 12702626 3.93% 93.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 2533807 0.78% 94.30% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 18448626 5.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 105871733 32.34% 32.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 108541066 33.15% 65.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 36996526 11.30% 76.79% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 11988281 3.66% 80.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 10398233 3.18% 83.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 21777635 6.65% 90.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 9735285 2.97% 93.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 2406783 0.74% 93.98% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 19702213 6.02% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 323575021 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 327417755 # Number of insts commited each cycle system.cpu.commit.COM:count 601856963 # Number of instructions committed system.cpu.commit.COM:loads 115049510 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4121096 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4120073 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 61591802 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 63088611 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.592670 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.592670 # CPI: Total CPI of All Threads +system.cpu.cpi 0.599437 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.599437 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 113443216 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 19248.740390 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7746.370369 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 112634831 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 15560393000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007126 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 808385 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 590181 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1690289000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001923 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 218204 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_accesses 116877204 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 19511.922037 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7693.277195 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 116024078 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 16646128000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007299 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 853126 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 634854 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1679227000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001868 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 218272 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32797.392555 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35638.802347 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 37116231 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 76584863381 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.059189 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2335090 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1996724 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 12058958995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008577 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 338366 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6528.414634 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 31935.176109 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34419.628617 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 37146976 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 73589663391 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.058410 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2304345 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1968193 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 11570226999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008521 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 336152 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7088.486726 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 21363.636364 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 316.462124 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 123 # number of cycles access was blocked +system.cpu.dcache.avg_refs 323.627554 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 113 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 802995 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 800999 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 235000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 152894537 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29313.182507 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24703.537731 # average overall mshr miss latency -system.cpu.dcache.demand_hits 149751062 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 92145256381 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.020560 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3143475 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2586905 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13749247995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003640 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 556570 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 156328525 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 28578.502032 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23897.692017 # average overall mshr miss latency +system.cpu.dcache.demand_hits 153171054 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 90235791391 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.020198 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3157471 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2603047 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13249453999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003547 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 554424 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999563 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.208277 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 152894537 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29313.182507 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24703.537731 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999568 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.232018 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 156328525 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 28578.502032 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23897.692017 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 149751062 # number of overall hits -system.cpu.dcache.overall_miss_latency 92145256381 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.020560 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3143475 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2586905 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13749247995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003640 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 556570 # number of overall MSHR misses +system.cpu.dcache.overall_hits 153171054 # number of overall hits +system.cpu.dcache.overall_miss_latency 90235791391 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.020198 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3157471 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2603047 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13249453999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003547 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 554424 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 470982 # number of replacements -system.cpu.dcache.sampled_refs 475078 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 471007 # number of replacements +system.cpu.dcache.sampled_refs 475103 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.208277 # Cycle average of tags in use -system.cpu.dcache.total_refs 150344193 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126612000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 335213 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 51119249 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 861 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4177292 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 689843810 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 144051375 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 122990983 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9853353 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 3386 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5413414 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 163070578 # DTB accesses +system.cpu.dcache.tagsinuse 4094.232018 # Cycle average of tags in use +system.cpu.dcache.total_refs 153756422 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126427000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 336082 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 53096224 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 870 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4174977 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 691367918 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 145684312 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 123209609 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 10007520 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 3007 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5427610 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 163170180 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 163012019 # DTB hits -system.cpu.dtb.data_misses 58559 # DTB misses +system.cpu.dtb.data_hits 163108618 # DTB hits +system.cpu.dtb.data_misses 61562 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 122259759 # DTB read accesses +system.cpu.dtb.read_accesses 122378622 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122237048 # DTB read hits -system.cpu.dtb.read_misses 22711 # DTB read misses -system.cpu.dtb.write_accesses 40810819 # DTB write accesses +system.cpu.dtb.read_hits 122354151 # DTB read hits +system.cpu.dtb.read_misses 24471 # DTB read misses _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
