Hi all,
I'm using M5 to configure a single L2$ multicore system.
The target architecture looks like following
------------------ -----------------
| core0 | | core |
------------------ -----------------
| | | |
|L1Inst$| | |L1Inst$| |
| | | |
----------------------------------------------- <----toL2Bus
|
| L2$ |
|
---------------------
|
| Phy mem|
In my target architecture, each core has its private L1 instruction cache,
but has no L1 data cache. Cores are sharing a L2$ on a Bus (toL2Bus). L2$
contains instructions and data.
my python config as following, most of the parts is as the same as the
configs/splash2/run.py
165 # ----------------------
166 # Create a system, and add system wide objects
167 # ----------------------
168 system = System(cpu = cpus, physmem = PhysicalMemory(),
169 membus = Bus(clock = busFrequency))
170
171 system.toL2bus = Bus(clock = busFrequency)
172 system.l2 = L2(size = options.l2size, assoc = 8)
173
174 # ----------------------
175 # Connect the L2 cache and memory together
176 # ----------------------
177
178 system.physmem.port = system.membus.port
179 system.l2.cpu_side = system.toL2bus.port
180 system.l2.mem_side = system.membus.port
181
182 # ----------------------
183 # Connect the L2 cache and clusters together
184 # ----------------------
185 for cpu in cpus:
186 ic = L1(size = options.l1size, assoc = 1)
187 cpu.icache = ic
188 cpu.mem = system.toL2bus
189 cpu.icache_port = ic.cpu_side
190 cpu.dcache_port = system.toL2bus.port
191 cpu._mem_ports = ['icache.mem_side']
192 cpu.connectMemPorts(system.toL2bus)
but when I did the simulation with timing model, the ticks when wrong.
$build/ALPHA_SE/m5.debug --trace-flags=MemoryAccess,Cache,Bus
configs/cacheco/singleL1.py -t -n 4 -b FFT
warn: Increasing stack size by one page.
10000: system.cpu2.icache: ReadReq 1cb64 hit
11000: system.toL2bus: recvTiming: src 0 dst -1 WriteReq 0xc5ff8
11000: system.l2: WriteReq c5ff8 miss
11000: system.toL2bus: The bus is now occupied from tick 11000 to 13000
12000: system.membus: recvTiming: src 1 dst -1 ReadExReq 0xc5fc0
12000: system.physmem: Read of size 64 on address 0xc5fc0
12000: system.membus: The bus is now occupied from tick 12000 to 13000
12001: system.membus: recvTiming: src 0 dst 1 ReadExResp 0xc5fc0 BUSY
12001: system.physmem-port0: Send failed, waiting on retry
13000: system.membus: Sending a retry to system.physmem-port0
13000: system.physmem-port0: Received retry
13000: system.membus: recvTiming: src 0 dst 1 ReadExResp 0xc5fc0
13000: system.l2: Handling response to c5fc0
13000: system.l2: Block for addr c5fc0 being updated in Cache
13000: system.l2: Block addr c5fc0 moving from state 0 to 7
13000: system.membus: The bus is now occupied from tick 13000 to 15000
13000: system.membus: Remove retry from list 0
16000: system.toL2bus: recvTiming: src 8 dst 0 WriteResp 0xc5ff8
16000: system.cpu2.icache: ReadReq 1cb68 hit
16000: system.toL2bus: The bus is now occupied from tick 16000 to
4831955816
17000: system.cpu2.icache: ReadReq 1cb6c hit
18000: system.cpu2.icache: ReadReq 1cb70 hit
19000: system.cpu2.icache: ReadReq 1cb74 hit
20000: system.cpu2.icache: ReadReq 1cb74 hit
21000: system.toL2bus: recvTiming: src 0 dst -1 ReadReq 0xba000 BUSY
4831955816: system.toL2bus: Sending a retry to system.cpu2-dport
4831955816: system.toL2bus: recvTiming: src 0 dst -1 ReadReq 0xba000
4831955816: system.l2: ReadReq ba000 miss
4831955816: system.toL2bus: The bus is now occupied from tick 4831955816 to
4831956816
4831955816: system.toL2bus: Remove retry from list 0
4831956816: system.membus: recvTiming: src 1 dst -1 ReadReq 0xba000
4831956816: system.physmem: Read of size 64 on address 0xba000
4831956816: system.membus: The bus is now occupied from tick 4831956816 to
4831958000
4831956817: system.membus: recvTiming: src 0 dst 1 ReadResp 0xba000 BUSY
4831956817: system.physmem-port0: Send failed, waiting on retry
4831958000: system.membus: Sending a retry to system.physmem-port0
4831958000: system.physmem-port0: Received retry
4831958000: system.membus: recvTiming: src 0 dst 1 ReadResp 0xba000
4831958000: system.l2: Handling response to ba000
4831958000: system.l2: Block for addr ba000 being updated in Cache
4831958000: system.l2: Block addr ba000 moving from state 0 to 7
4831958000: system.membus: The bus is now occupied from tick 4831958000 to
4831960000
4831958000: system.membus: Remove retry from list 0
4831961000: system.toL2bus: recvTiming: src 8 dst 0 ReadResp 0xba000
4831961000: system.cpu2.icache: ReadReq 1cb78 hit
4831961000: system.toL2bus: The bus is now occupied from tick 4831961000 to
4831955832
m5.debug: build/ALPHA_SE/sim/simulate.cc:67: SimLoopExitEvent*
simulate(Tick): Assertion `curTick <= mainEventQueue.nextTick() && "event
scheduled in the past"' failed.
Program aborted at cycle 4831961000
I can't figure out what cause this situation. But one thing confused me is
the param dcache in cpu. Because in my model, I didn't have any direct
connect data cache to cpu. Each core have to share a single L2$ on a bus.
Do I need to rebuild the cpu mode? or anything I missed?
Thanks,
Dave.
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